SL28SRC02BZI Silicon Laboratories Inc, SL28SRC02BZI Datasheet - Page 2

• Manufacturer Part Number: SL28SRC02BZI
• Description: Clock Generators & Support Products PCIE Clk Gen Xin 14M -->4 PCIE out Gen3
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28SRC02BZI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.1
Pin Definitions
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
.
Table 1. Command Code Definition
Pin No.
(6:0)
10
11
12
13
14
15
16
17
18
19
20
Bit
1
2
3
4
5
6
7
8
9
7
VDD
SDATA
SCLK
VDD
VSS
VDD
VSS
SRC1
SRC1#
VSS
SRC2
SRC2#
VDD
VDD
VSS
VDD
SSON
VSS
XOUT
XIN
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Name
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
O, SE 14.318 MHz Crystal output.
PWR
PWR
PWR
PWR
PWR
PWR
Type
GND
GND
GND
GND
GND
I/O
I
I
I
3.3V Power supply
SMBus compatible SDATA.
SMBus compatible SCLOCK.
3.3V power supply
Ground
3.3V power supply
Ground
Ground
3.3V power supply
3.3V power supply
Ground
3.3V power supply
3.3V LVTTL input for enabling spread spectrum clock
0 = Disable, 1 = Enable (-0.5% SS)
External 10K ohm pull-up or pull-down resistor required
Ground
14.318 MHz Crystal input.
Description
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
Description
SL28SRC02
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