LAN89218AQ SMSC, LAN89218AQ Datasheet - Page 133

• Manufacturer Part Number: LAN89218AQ
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
Chapter 6 Timing Diagrams
SMSC LAN89218
6.1
6.1.1
Read Cycles:
Write Cycles:
The LAN89218 supports the following host cycles:
Note: Unless otherwise noted, timing specifications assume a load capacitance of 25pF and are valid
Special Restrictions on Back-to-Back Write/Read Cycles
It is important to note that there are specific restrictions on the timing of back-to-back write-read
operations. These restrictions concern reading the control registers after any write cycle to the
LAN89218 device. In many cases there is a required minimum delay between writing to the LAN89218,
and the subsequent side effect (change in the control register value). For example, when writing to the
TX Data FIFO, it takes up to 135 ns for the level indication to change in the TX_FIFO_INF register.
In order to prevent the host from reading stale data after a write operation, minimum wait periods must
be enforced. These periods are specified in
processor is required to wait the specified period of time after any write to the LAN89218 before
reading the resource specified in the table. These wait periods are for read operations that immediately
follow any write cycle. Note that the required wait period is dependant upon the register being read
after the write.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum write-to-read timing restriction is met.
are required before reading the register indicated. The number of BYTE_TEST reads in this table is
based on the minimum timing for Tcycle (45 ns). For microprocessors with slower busses the number
of reads may be reduced as long as the total time is equal to, or greater than the time specified in the
table. Note that dummy reads of the BYTE_TEST register are not required as long as the minimum
time period is met.
Host Interface Timing
PIO Reads (nCS or nRD controlled)
PIO Burst Reads (nCS or nRD controlled)
RX Data FIFO Direct PIO Reads (nCS or nRD controlled)
RX Data FIFO Direct PIO Burst Reads (nCS or nRD controlled)
PIO writes (nCS and nWR controlled)
TX Data FIFO direct PIO writes (nCS or nWR controlled)
over the operating conditions specified in
DATASHEET
133
Table 6.1, "Read After Write Timing
Table 6.1
Section 7.2, "Operating
also shows the number of dummy reads that
Conditions**".
Revision 1.3 (02-23-10)
Rules". The host