COM90C66LJP

Manufacturer Part NumberCOM90C66LJP
DescriptionCOM90C66LJPARCNET Controller/Transceiver with AT Interface and On-Chip RAM
ManufacturerSMSC Corporation
COM90C66LJP datasheet
 


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ARCNET Controller/Transceiver with
AT Interface and On-Chip RAM
ARCNET LAN Controller/Transceiver/
Support Logic/Dual-Port RAM
Integrates SMSC COM90C65 with 16-Bit
Data Bus, Dual-Port RAM, and Enhanced
Diagnostics Circuitry
Includes IBM
PC/AT
Bus Interface
Circuitry
Supports 8- and 16-Bit Data Buses
Full 2K x 8 On-Chip Dual-Port Buffer RAM
Zero Wait State Arbitration for Most AT
Buses
SMSC COM90C26 Software Compatible
Command Chaining Enhances Performance
Supports Memory Mapped and Sequential
I/O Mapped Access to the Internal RAM
Buffer
The SMSC COM90C66 is a special purpose
communications controller for interconnecting
processors and intelligent peripherals using the
ARCNET Local Area Network. The COM90C66
is unique in that it integrates the core ARCNET
logic found in Standard Microsystems' original
COM90C26 and COM90C32 with an on-chip 2K
x 8 RAM, as well as the 16-bit data bus interface
for the IBM PC/AT. Because of the inclusion of
the RAM buffer in the COM90C66, a complete
ARCNET node can be implemented with only
one
or
two
additional
ICs
(8-
applications, respectively) and a media driver
circuit. The ARCNET core remains functionally
untouched,
eliminating
validation
compatibility concerns. The enhancements exist
in the integration and the performance
Data Sheet with Erratas for
Rev. B and Rev. D devices
FEATURES
Compatible with the SMSC HYC9058/68/ 88
(COAX and Twisted Pair Drivers)
Token Passing Protocol with Self
Reconfiguration Detection
Variable Data Length Packets
16 Bits CRC Check/Generation
Includes Address Decoding Circuitry for On-
Chip RAM, PROM and I/O
Supports up to 255 Nodes
Contains Software Accessible Node ID
Register
Compatible with Various Topologies (Star,
Tree, Bus, ...)
On-Board Crystal Oscillator and Reset
Circuitry
Low Power CMOS, Single +5V Supply
GENERAL DESCRIPTION
device. Maximum integration has been achieved
by including the 2K x 8 RAM buffer on the chip,
providing the immediate benefits of a lower
device pin count and less board components.
The performance is enhanced in four ways: a
16-bit data bus for operation with the IBM PC/AT;
a zero wait state arbitration mechanism, due
partly to the integration of the RAM buffer on-
chip; the ability of the device to do consecutive
transmissions and receptions via the Command
Chaining operation; and improved diagnostics,
or
16-bit
allowing the user to control the system more
efficiently. For most AT compatibles, the device
handles zero wait state transfers.
and
ARCNET is a registered trademark of Datapoint Corporation
IBM, AT, PC/AT and Micro Channel are registered trademarks of
of the
International Business Machines Corporation
1
COM90C66

COM90C66LJP Summary of contents