COM90C66LJP SMSC Corporation, COM90C66LJP Datasheet
COM90C66LJP
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COM90C66LJP Summary of contents
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ARCNET Controller/Transceiver with AT Interface and On-Chip RAM ARCNET LAN Controller/Transceiver/ Support Logic/Dual-Port RAM Integrates SMSC COM90C65 with 16-Bit Data Bus, Dual-Port RAM, and Enhanced Diagnostics Circuitry Includes IBM PC/AT Bus Interface Circuitry Supports 8- and 16-Bit Data Buses Full ...
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FEATURES ........................................................................................................................................................................ 1 GENERAL DESCRIPTION ................................................................................................................................................ 1 PIN CONFIGURATION ...................................................................................................................................................... 3 DESCRIPTION OF PIN FUNCTIONS ............................................................................................................................... 4 PROTOCOL DESCRIPTION ............................................................................................................................................. 9 NETWORK PROTOCOL ........................................................................................................................................... 9 NETWORK RECONFIGURATION ........................................................................................................................... 9 BROADCAST MESSAGES ..................................................................................................................................... 10 EXTENDED TIMEOUT FUNCTION ........................................................................................................................ 10 LINE PROTOCOL ...
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For other machines, the IOCHRDY signal may be briefly negated to give the device the extra time necessary to support the faster machines. Aside from the implementation of a 16-bit data bus interface, the remaining bus interface logic is identical ...
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DESCRIPTION OF PIN FUNCTIONS PLCC PIN NO. NAME SYMBOL 75-84, 2- Address 0-19 A0-A19 11 13-20, Data 0-15 D0-D15 22-29 63, 62 nTransceiver nTOPL, Direction nTOPH Control 71 I/O Channel IOCHRDY Ready 12 Address AEN Enable 74 Address Latch BALE ...
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DESCRIPTION OF PIN FUNCTIONS PLCC PIN NO. NAME SYMBOL 66 nMemory Read nMEMR 67 nMemory nMEMW Write 52 Reset In RESETIN 53 nROM Enable nENROM 54 nROM Select nPROM 30 Interrupt INTR Request 72 nZero Wait n0WS State 70 nMemory ...
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DESCRIPTION OF PIN FUNCTIONS PLCC PIN NO. NAME SYMBOL 69 nI/O 16-Bit nIOCS16 Chip Select 73 nSystem Bus nSBHE High Enable TRANSMISSION MEDIA INTERFACE 56, 55 nPulse 2, nPULSE 2, nPulse 1 nPULSE 1 57 Receive In RXIN 51-47 Memory ...
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DESCRIPTION OF PIN FUNCTIONS PLCC PIN NO. NAME SYMBOL 33, 34 Crystal XTAL1, Oscillator XTAL2 59 CA Clock CACLK 58 Clock CLK 1, 43 Power Supply V cc 21, 68 Ground GND 60-61 No Connect NC DESCRIPTION An external parallel ...
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Power On Reconfigure Send Timer has Reconfigure Timed Out Burst Read ID* From Switches Write ID to RAM Buffer Set NID=ID Invitation Y Start to Transmit to Reconfiguration this ID? Timer (840 mS TA? Y Transmit NAK Transmit ...
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NETWORK PROTOCOL Communication on the network is based on a token passing protocol. Establishment of the network configuration and management of the network protocol are handled entirely by the COM90C66's internal microcoded sequencer. A processor or intelligent peripheral transmits data ...
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The time required RECONFIGURATION depends on the number of nodes in the network, the propagation delay between nodes, and the highest ID number on the network, but will be in the range mS. ...
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The line idles in a spacing (logic "0") condition. A logic "0" is defined as no line activity and a logic "1" is defined as ...
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Acknowledgements An Acknowledgement is used to acknowledge reception of a packet affirmative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST An ACK (ACKnowledgement--ASCII code 86 HEX) character ALERT BURST ACK ...
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TRANSMISSION MEDIA INTERFACE The right half of Figure 2 illustrates the COM90C66 interface to the transmission media used to connect the node to the network. The HYC9058/68/88 may be used to drive the media. During transmission, the COM90C66 transmits a ...
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IRQ2-IRQ5, IRQ7 8 7 IBM INTR AT BUS AEN AEN BALE BALE nIOR nIOR nIOW nIOW nMEMR nMEMR nMEMW nMEMW RSTDRV RESET IN IOCHRDY IOCHRDY 1 2 nOWS 1 nOWS 2 ...
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IOS0-2 MS0-4 A0-A19 nENROM nPROM ADDRESS AEN DECODING BALE CIRCUITRY nTOPL nTOPH D0-D15 STATUS/ INTR COMMAND REGISTER RESET RESET IN LOGIC nMEMR nMEMW I/O CHANNEL nIOR READY nIOW AND BUS nMEMCS16 ARBITRATION nIOCS16 CIRCUITRY IOCHRDY nSBHE nOWS FIGURE 3 - ...
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BALE A19 A18 A17 A16 Transparent A15 Latch A14 A13 A12 A11 FIGURE 4 – MEMORY SELECTOR nENROM BALE A19 A18 A17 Transparent A16 Latch A15 A14 A13 I/O 16K X 8 Mode, A13 is a Don't Care ...
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FIGURE 7 - 16K MEMORY SEGMENT CHOSEN BY MS0-MS4 (Memory Mapped Mode) SHORT PACKET FORMAT (256 OR 512 BYTE PAGE) SID 0 DID 1 COUNT = 256-N 2 NOT USED COUNT DATA BYTE 1 DATA BYTE 2 DATA BYTE N-1 ...
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Table 1 – User Configuration of Memory Map DECODED BITS FOUND IN DATA REGISTER MS4 MS3 MS2 MS1 MS0 ...
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ADDRESS DECODING The COM90C66 includes address decoding circuitry that compares the value of the Address Bus to the address range selected by the Memory Select (MS0-MS4) and I/O Select (IOS0-IOS2) pins in order to Table 2 - User Configuration of ...
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Table 3 – Read Register Summary REGISTER MSB STATUS DIAG. MYRECON X RCVACT TOKEN STATUS CONFIG- CCHEN DECODE ET1 16EN URATION I/O SELECT 0 0 I/O5 MEMORY MEM7 MEM6 MEM5 SELECT NODE NID7 NID6 NID5 ID RESERVED ...
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Table 4 – Write Register Summary ADDRESS MSB CCHEN DECODE ET1 16EN NID7 NID6 NID5 ...
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The IOS2-IOS0 pins are decoded through Decoder to generate a 12-bit value. These 12 bits are compared to the A15-A4 lines of the address bus in order to determine which block of 16 I/O ...
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BIT BIT NAME SYMBOL 7 Receiver Inhibited RI 6 (not used) 5 (not used) 4 Power On Reset POR 3 Test TEST 2 Reconfiguration RECON 1 Transmitter TMA Message Acknowledged 0 Transmitter TA Available Table 5 - Status Register DESCRIPTION ...
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Table 6 - Diagnostic Status Register BIT BIT NAME SYMBOL 7 My Reconfiguration MY- RECON 5 Receive Activity RCVACT This bit, if high, indicates that receive activity (data transition) 4 Token Seen TOKEN 6, (not used) 3-0 Table 7 - ...
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Table 7 - Command Register WRITTEN DATA COMMAND NAME 000n n011 ENABLE TRANSMIT FROM PAGE nn b00n n100 ENABLE RECEIVE TO PAGE nn 0000 c101 DEFINE CONFIGURATION 000r p110 CLEAR FLAGS 0000 1000 CLEAR RECEIVE INTERRUPT DESCRIPTION This command prepares ...
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Table 8 - Configuration Register BIT BIT NAME SYMBOL 7 16-Bit Enable 16EN 6 Command CCHEN Chaining Enable 5 Decode Mode DECODE In I/O Mapped applications, this bit is used to choose 4, 3 Extended ET1, ET2 These bits allow ...
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Table 8 - Configuration Register BIT BIT NAME SYMBOL 2 Wait State WAIT 1 I/O Access IO- ACCESS 0 Transmitter Off TXOFF Table 9 - Address Pointer Low Register BIT BIT NAME SYMBOL 7-0 Address 7-0 A7-A0 Table 10 - ...
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Configuration Register The Configuration Register is a read/write register which can be accessed microprocessor to configure the different modes of the COM90C66. The register contents are as in Table 8. The Configuration Register defaults to the value 0001 1100 upon ...
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Address Pointer Low and High Registers These read/write registers are each 8-bits wide and are used in I/O Mapped Mode only. These bits contain undefined data upon software or hardware reset. The contents of the Address Pointer Registers are defined ...
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The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM90C66 puts the local ID in this location, therefore not necessary to write into this location. ...
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The fourth possibility non-traditional response is received (some pattern other than ACK or NAK, such as noise). In this case, the token is not passed onto the next node, which causes the Lost Token Timer of the ...
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FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM90C66 to be compatible with previous SMSC ARCNET devices, the device defaults to the non-chaining mode. In ...
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Transmit Command Chaining When the processor issues the first ENABLE TRANSMIT TO PAGE nn command, COM90C66 responds in the usual manner by resetting the TA and TMA bits to prepare for the transmission from the specified page. The TA bit ...
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Typically, the interrupt service routine will read the Status Register. point, the RI bit will be found logic "1". After reading the Status Register, the CLEAR RECEIVE INTERRUPT command is issued, thus resetting the TRI bit ...
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A software reset is generated microprocessor accesses I/O locations Upon reset, the transmitter portion of the device is ...
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Hardware or Software Reset Internal POR nMEMR, nMEMW, nIOR, nIOW Microsequencer POR Internal Reset 1 During this time, the microsequencer is being reset and the transmitter portion of the device is disabled. 2 During this time, the microsequencer writes D1H ...
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OFH and OEH (Address Pointer High and Low Registers). processor then reads/writes from/to address 0CH (for 8-bit) or OCH and ODH (for 16 bit) the data found/to be placed at that address. If the Auto ...
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Table 11 - 16-Bit Memory Mapped Decode n DECODE n ENROM MODE RAM MEMCS16 128K The internal latches of the COM90C66 go transparent on BALE high and latch on ...
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Data Register I/O Address ODH High D0-D15 Address Pointer Register I/O Address 0FH High 11-Bit Counter FIGURE 11 - SEQUENTIAL I/O MAPPED MEMORY ACCESS OPERATION Memory I/O Address 0CH Data Bus Low 16 I/O Address 0EH Low Memory Address Bus ...
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A11-A19 SA11-SA19 TRANSPARENT LATCH BALE Falling Edge of BALE Latches the Address Rising Edge of BALE Makes Latch Transparent LA17-LA19 3 5 MS0-MS4 FIGURE 12 – nMEMCS16 GENERATION AEN 12 TRANSPARENT SA4-SA15 LATCH BALE IOS0-IOS2 2 SA2-SA3 FIGURE 12A ...
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IOCHRDY signal for two XTAL1 clocks. Note that by timing the ready circuitry from the XTAL1 clock, the IOCHRDY signal is timed in absolute time rather than relative to the ...
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Data Register space is desired, the A0 bit should be forced to a logic "0" and A1-A10 will be used to load the Address Pointer Register. A single byte ...
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NODE ID LOGIC The Node ID code generated by the external Node ID Select Switches is used to identify this particular COM90C66. The code, which is input by the COM90C66 in parallel format, is used by the COM90C66 during transmission, ...
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The RCVACT and TOKEN bits of the Diagnostic Status Register may help the troubleshoot the network or the node. If Table 15 - Diagnostic Bits for Troubleshooting Network Activity RCVACT TOKEN ...
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OSCILLATOR The COM90C66 incorporates on-board circuitry which, in conjunction with an external parallel resonant crystal, forms an oscillator. oscillator frequency may vary from 8 MHz to 20 MHz to allow for a variable data rate from 1.0 Mbps to 2.5 ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS * Operating Temperature Range ......................................................................................... 0 Storage Temperature Range ....................................................................................... -55 Lead Temperature (soldering, 10 seconds) ............................................................................... +325 Positive Voltage on any pin, with respect to ground ................................................................ V Negative Voltage on any pin, with ...
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DC ELECTRICAL CHARACTERISTICS (T PARAMETER SYMBOL Low to High Threshold V ILH Input Voltage (RESET, AEN, nIOR, nIOW, nMEMR, nMEMW) High to Low Threshold V IHL Input Voltage (RESET, AEN, nIOR, nIOW, nMEMR, nMEMW) Low Output Voltage 1 V OL1 ...
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CAPACITANCE ( 1MHz Output and I/O pins capacitive load specified as follows: PARAMETER SYMBOL Input Capacitance C IN Output Capacitance 1 C OUT1 (All outputs except IOCHRDY, n0WS, nMEMCS16, nIOCS16, INTR) ...
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The AC parameters in Figures 14-26 are preliminary. Enhancements will follow. nMEMR, nMEMW, nIOR, or nIOW t2 nOWS** t4 IOCHRDY** Parameter t1 Control Signal Pulse Width t2 Control Signal Low to nOWS Low t3 Control Signal High to nOWS High ...
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A0-A19 nSBHE t1 BALE nMEMR t3 D0-D7 or D0-D15 nTOPH, nTOPL t6 nMEMCS16 t7 (Unlatched) nMEMCS16 (Latched) Parameter t1 Address, nSBHE Set Up to BALE Low* t2 Address, nSBHE Hold after BALE Low* t3 Address, nSBHE Set Up to nMEMR ...
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A0-A19 nSBHE t1 BALE nMEMW t3 D0-D7 or D0-D15 nTOPL t5 nMEMCS16 (Unlatched) t6 nMEMCS16 (Latched) Parameter Address, nSBHE Set Up to BALE Low * t1 t2 Address, nSBHE Hold after BALE Low * Address, nSBHE Set Up to nMEMW ...
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AEN A0-A15, nSBHE t1 BALE nIOR t3 or D0-D7 D0-D15 nTOPH, nTOPL t6 nIOCS16 Parameter Address, nSBHE Set Up to BALE Low * t1 Address, nSBHE Hold after BALE Low * t2 Address, nSBHE, AEN Set Up to nIOR Low ...
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AEN A0-A15, nSBHE t1 BALE nIOW t3 D0-D7 or D0-D15 nTOPH nTOPL t5 nIOCS16 Parameter t1 Address, nSBHE Set Up to BALE Low * t2 Address, nSBHE Hold after BALE Low * t3 Address, nSBHE, AEN Set Up to nIOW ...
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A0-A19 t1 BALE nMEMR t3 nPROM ** nTOPL IOCHRDY Parameter t1 Address Set Up to BALE Low * t2 Address Hold after BALE Low * t3 Address, Set Up to nMEMR Low t4 nMEMR Low to nPROM Low nMEMR Low ...
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AEN A0-A15 t1 BALE nIOW t3 nPROM ** IOCHRDY Parameter t1 Address Set Up to BALE Low * t2 Address Hold after BALE Low * t3 Address, AEN Set Up to nIOW Low t4 nIOW Low To nPROM Low t5 ...
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BALE (tied high) A0-A19 nMEMR nMEMW nIOR nIOW Parameter t1 Control Signal High to Address Invalid In the case of Latched Addresses, when BALE is tied high, disregard t1 and t2 in Figures 15-20. Instead, use the above timing. FIGURE ...
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Parameter t1 nPULSE1, nPULSE2 Pulse Width t2 nPULSE1, nPULSE2 Period t3 nPULSE1, nPULSE2 Overlap *NOTE (crystal period) for clock frequencies other than 20 MHz. **NOTE (crystal ...
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RXIN Parameter t1 RXIN Pulse Width t2 RXIN Period * NOTE: This period applies to data of two consecutive one's. FIGURE 23 - RECEIVE TIMING t2 min typ max units 10 nS 400 nS* 58 ...
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XTAL1 Parameter t1 Input Clock High Time t2 Input Clock Low Time t3 Input Clock Period f Input Clock Frequency FIGURE 24 – TTL INPUT CLOCK TIMING ON XTAL1 PIN t1 CLK Parameter t1 Output Clock High Time t2 ...
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RESET INTR nTXLED nBSLED Parameter t1 Reset Pulse Width t2 INTR Inactive Time t3 nTXLED Active (Low) t4 nBSLED Active (Low) FIGURE 26 - RESET, INTERRUPT, AND LED TIMING min typ 120 200 650 320 60 ...
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G PIN DIM 84L A .165-.179 A1 .095-.109 D 1.185-1.195 D1 1.150-1.156 D2 1.090-1.130 1.000 D3 F .050 TYP G .045 TYP J .010 E .047-.053 R .025-.045 B .013-.021 B1 .027 .020-.045 C FIGURE ...
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DATA SHEET ERRATA FOR REVISION B COM90C66 The Revision B device does not operate properly in 8-bit mode. Therefore, any reference to 8-bit - operation should be disregarded. The Revision B device asserts the nn0WS signal on any memory read ...
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DATA SHEET ERRATA FOR REVISION B COM90C66 PAGE SECTION/FIGURE/ENTRY 4 Description of Pin Functions - n0WS 13 Figure 2 - Bus Interface 20,21, Tables Configuration 25,37, Register Bit 7 (16EN) and Bit 5 39 (DECODE); Tables ...
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DATA SHEET ERRATA FOR REVISION D COM90C66 The Revision D device contains 16-bit detection circuitry on the input of pin 60 to allow the device - to power up in 16-bit mode. writing to the Configuration Register, the device defaults ...
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DATA SHEET ERRATA FOR REVISION D COM90C66 PAGE SECTION/FIGURE/ENTRY 2,6,13 Pin Configuration Description of Pin Functions - Pin 60; Figure 2 - System Block Diagram - Pin 60 25 Table 8 - Configuration Register - Bit 7 CORRECTION - Pin ...
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PAGE SECTION/FIGURE/ENTRY 40 8-Bit vs. 16-Bit Accesses 39 Figure 12 - nMEMCS16 Generation 49,50 Figure 15 - Read RAM Cycle -t7, t11; Figure 16 - Write RAM Cycle - t6 Figure 12A - nIOCS16 Generation 51,52 Figure 17 ...
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PAGE SECTION/FIGURE/ENTRY 3 Description of Pin Functions, Pin 53 26 Configuration Register, Bit 2 37,40 Wait State Details section; Table 13 - IOCHRDY and n0WS Signal Behavior 48 Figure 14 - Zero Wait State and IOCHRDY Timing 3 Description of ...
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PAGE SECTION/FIGURE/ENTRY 49, 50, 53 Figures 15,16,19 - Read RAM Cycle, Write RAM Cycle, Read PROM Cycle CORRECTION For Revision D, a new timing parameter should exist: Address, SBHE hold after Control Low...20 nsec minimum. This parameter is only required ...
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Modified Version of Pages 16 and 41 for Rev. D COM90C66 Only. nMEMR,nMEMW BALE A19 A18 A17 A16 Transparent Transparent A15 Latch Latch A14 A13 A12 A11 FIGURE 4 - MEMORY SELECTOR nENROM nMEMR BALE A19 A18 A17 Transparent Transparent ...
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Modified Version of Page 40 for Rev. D COM90C66 Only. SA11-SA19 A11-A19 LA17-LA19 3 5 MS0-MS4 FIGURE 12 – nMEMCS16 GENERATION AEN SA4-SA15 IOS0-IOS2 2 SA2-SA3 FIGURE 12A - nIOCS16 GENERATION 9 COMPARATOR (for 2K segment) 5 COMPARATOR (for 128K ...
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Modified Version of Page 50 for Rev. D COM90C66 Only. A0-A19 VALID nSBHE t1 BALE nMEMR t3 D0-D7 or D0-D15 nTOPH, nTOPL t6 nMEMCS16 t7 (Unlatched) nMEMCS16 (Latched) Parameter t1 Address, nSBHE Set Up to BALE Low * t2 Address, ...
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Modified Version of Page 51 for Rev. D COM90C66 Only. A0-A19 nSBHE t1 BALE nMEMW t3 D0-D7 or D0-D15 nTOPL t5 nMEMCS16 (Unlatched) t6 nMEMCS16 (Latched) Parameter t1 Address, nSBHE Set Up to BALE Low * t2 Address, nSBHE Hold ...
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Modified Version of Page 52 for Rev. D COM90C66 Only. AEN A0-A15, nSBHE t1 BALE nIOR t3 or D0-D7 D0-D15 nTOPH, nTOPL t6 nIOCS16 Parameter Address, nSBHE Set Up to BALE Low * t1 Address, nSBHE Hold after BALE Low ...
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Modified Version of Page 53 for Rev. D COM90C66 Only. AEN A0-A15, nSBHE t1 BALE nIOW t3 D0-D7 or D0-D15 nTOPH nTOPL t5 nIOCS16 Parameter t1 Address, nSBHE Set Up to BALE Low * t2 Address, nSBHE Hold after BALE ...
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Modified Version of Page 54 for Rev. D COM90C66 Only. A0-A19 t1 BALE nMEMR t3 nPROM ** nTOPL IOCHRDY Parameter t1 Address Set Up to BALE Low * t2 Address Hold after BALE Low * t3 Address, Set Up to ...
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STANDARD MICROSYSTEMS CORP. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be ...