LAN91C110 SMSC Corporation, LAN91C110 Datasheet
LAN91C110
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LAN91C110 Summary of contents
Page 1
... An IEEE-802.3 compliant Media Independent Interface (MII) provided on the network side of the LAN91C110. The MII interface allows the use of a wide range of MII compliant Physical Layer (PHY) devices to be used with the LAN91C110. The LAN91C110 also provides an interface to the two-line MII serial management protocol. ...
Page 2
... CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ORDERING INFORMATION ...
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... ACKAGE UTLINE ABLE PIN CONFIGURATION .............................................................................................................................4 IGURE LAN91C110 BLOCK DIAGRAM ..............................................................................................................8 IGURE LAN91C110 SYSTEM DIAGRAM............................................................................................................8 IGURE LAN91C110 INTERNAL BLOCK DIAGRAM WITH DATAPATH......................................................12 IGURE DATA PACKET FORMAT ......................................................................................................................13 IGURE INTERRUPT STRUCTURE .....................................................................................................................31 IGURE INTERRUPT SERVICE ROUTINE .........................................................................................................39 IGURE INTR ....................................................................................................................................................40 ...
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... RD5 27 RD4 28 GND 29 RD3 30 RD2 31 RD1 32 VDD 33 RD0 34 RD15 35 RD14 36 SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications LAN91C110 144 Pin TQFP FIGURE 1 - PIN CONFIGURATION Page 4 108 A9 A8 107 A7 106 A6 105 104 A5 A4 103 A3 102 ...
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... AEN signals. IS Input. Address strobe. For systems that require address latching. The rising edge of nADS indicates the latching moment of A[1:15] and AEN. All LAN91C110 internal functions of A[1:15] and AEN are latched. O4 Output. The interrupt output is enabled by selecting the appropriate routing bits (INT SEL the Configuration Register ...
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... MII management data output. O4 MII management clock. I with Input. Indicates a code error detected by PHY. pulldown Used by the LAN91C110 to discard the packet being received. The error indication reported for this event is the same as a bad CRC (Receive Status Word bit 13). Page 6 Rev. 09/05/02 ...
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... FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications BUFFER TYPE O4 Output. Chip Select provided for mapping of PHY functions into LAN91C110 decoded space. Active on accesses to LAN91C110’s eight lower addresses when the BANK SELECTED is 7. +5V power supply pins. +5V analog power supply pins. Ground pins. Analog ground pin. ...
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... FIGURE 2 - LAN91C110 BLOCK DIAGRAM SYSTEM BUS ADDRESS ADDRESS CONTROL CONTROL DATA DATA RA SRAM 32kx8 FIGURE 3 - LAN91C110 SYSTEM DIAGRAM SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ARBITER DIRECT MEMORY ACCESS MEMORY MANAGEMENT UNIT RAM 25 MHz LAN91C110 ...
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... The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These FIFOs can be accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not Ready' whenever a cycle is initiated that cannot be satisfied by the present state of the FIFO. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications FUNCTIONAL DESCRIPTION Page 9 Rev ...
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... With ISA, the read and write operations are controlled by the edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle. The leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C110 clock and, therefore, asynchronous to the bus. ...
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... The MII SELECT bit in the CONFIG REGISTER must always be set for proper chip function. Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running clocks. The LAN91C110 will not rely on the presence of TX25 and RX25 during reset and will use its own internal clock whenever a timeout on TX25 is detected. ...
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... Control Control 8-16 bit Bus Interface Address Control Unit WR FIFO Data RD FIFO FIGURE 4 - LAN91C110 INTERNAL BLOCK DIAGRAM WITH DATAPATH SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Control Control Control Arbiter MMU DMA TX/RX FIFO Pointer TX Data ...
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... COUNT WORD, the DATA AREA and the CONTROL BYTE. The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications 2nd Byte ...
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... On transmit, all bytes are provided by the CPU, including the source address. The LAN91C110 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C110 treated transparently as data both for transmit and receive operations. ...
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... Regardless of the functional description, all registers can be accessed as doublewords, words or bytes. The default bit values upon hard reset are highlighted below each register. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications HASH VALUE 5-0 ...
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... BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the register bank in use. The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C110. The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2. ...
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... FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C110 will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted ...
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... Set when 16 collisions are detected for a transmit frame. TXENA bit in TCR is reset. Cleared when TXENA is set high. LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit frame. SMSC DS – LAN91C110 REV. B NAME TYPE READ ONLY ...
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... SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C110’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). Otherwise recognizes a receive frame as soon as carrier sense is active ...
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... FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory. The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command. MEMORY SIZE - This register can be read to determine the total memory size. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME ...
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... The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the Memory Size Multiplier. M=2 for the LAN91C110. A value of 04h in the lower byte of the MCR is equal to one 2K page (4 * 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only when the entire memory is being reserved for transmit (i.e., low byte of MCR = FFh). SMSC DS – ...
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... MII SELECT - Used to select the network interface port. When set, the LAN91C110 will use its MII port and interface a PHY device at the nibble rate. This bit must always be set for proper chip function. NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not ready for a transfer ...
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... BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 BANK 1 OFFSET NAME A Reserved. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TYPE READ/WRITE ADDRESS ADDRESS ADDRESS ADDRESS 3 ...
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... TE ENABLE bit. TE ENABLE defaults low (disabled). Transmit Error is any condition that clears TXENA with TX_SUC staying low as described in the EPHSR register. Reserved 2-0: These reserved bits must always be written to as zero(0). SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TYPE ...
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... Namely N2, N1 will request 2 * 256 = 512 bytes. A shift-based divide by 256 of the packet length yields the appropriate value to be used as N2, N1, N0. Immediately generates a completion code at the ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion. N2, N1, N0 are ignored by the LAN91C110 but should be implemented in LAN91C110 software drivers for LAN9000 compatibility. 010 ...
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... Note 1: Bits N2,N1,N0 bits are ignored by the LAN91C110 but should be used for command 0 to preserve software compatibility with the LAN91C92 and future devices. They should be zero for all other commands. Note 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them ...
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... Note: For software compatibility with future versions, the value read from each FIFO register is intended to be written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively). SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
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... Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value. BANK 2 OFFSET 8 THROUGH Bh DATA REGISTER SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE READ/WRITE NOT EMPTY is a read only bit NOT READ ETEN EMPTY ...
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... DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register. This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C110 regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre- fetched from memory into the read FIFO ...
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... RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. Receive Interrupt is cleared when RX FIFO is empty. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 30 ...
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... SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications FIGURE 6 - INTERRUPT STRUCTURE Page 31 Rev. 09/05/02 ...
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... With the proper memory structure, the search is limited to comparing only the multicast addresses that have the actual hash value in question. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
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... LOW CHIP BYTE 1 0 CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE READ/WRITE ...
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... Whenever the number of bytes written in memory for the presently received packet exceeds the ERCV THRESHOLD, ERCV INT bit of the INTERRUPT STATUS REGISTER is set. BANK7 OFFSET 0 THROUGH 7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C110 when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE LOW BYTE SMSC DS – LAN91C110 REV. B ...
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... CYCLE AEN=0 A3=0 A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 Otherwise SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications nCSOUT Driven low. Transparently latched on nADS rising edge. High High Page 35 LAN91C110 DATA BUS Ignored on writes. Tri-stated on reads. ...
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... STATUS Register, write the packet number of the current packet to the Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAC SIDE The enqueued packet will be transferred to the ...
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... STATUS Register, write the packet number of the current packet to the Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAC SIDE The enqueued packet will be transferred to the ...
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... CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAC SIDE A packet is received with matching address. ...
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... Packet Available for Transmission? Yes Call ALLOCATE Call EPH INTR FIGURE 7 - INTERRUPT SERVICE ROUTINE SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ISR Save Bank Select & Address Ptr Registers Mask SMC91C100FD Interrupts Read Interrupt Register ...
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... SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes No Destination Multicast? Read Words from RAM for Address Filtering Address Yes No Filtering Pass? Yes No Status Word ...
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... SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TX INTR Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg. Write Into Packet Number Register Write Address Pointer Register Read Status Word from RAM Yes ...
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... TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) FIGURE 10 - TXEMPTY INTR (ASSUMES AUTO RELEASE OPTION SELECTED) SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR ...
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... Write Source Address into Copy Remaining TX Data Set "Ready for Packet" Flag Return Buffers to Upper Layer FIGURE 11 - DRIVE SEND AND ALLOCATE ROUTINES SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ALLOCATE Issue "Allocate Memory" Command to MMU ...
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... Note that with the memory management built into the LAN91C110, the CPU can dynamically program this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory) ...
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... RELEASE=1 the CPU is not provided with the packet numbers that completed successfully. Note : The pointer register is shared by any process accessing the LAN91C110 memory. In order to allow processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt ...
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... CLK Low Input Level High Input Level Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications SYMBOL MIN TYP MAX V 0.8 ILI 2 ...
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... Low Output Level High Output Level Output Leakage OD16 Type Buffer Low Output Level Output Leakage Supply Current Active Supply Current Standby SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications SYMBOL MIN TYP MAX V 0 ...
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... 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance CAPACITIVE LOAD ON OUTPUTS ARDY, D0-D15 240 pF All other outputs 45 pF SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications = 5V CC LIMITS MIN TYP MAX ...
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... Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t8 A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE1 Hold after nADS Rising SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TIMING DIAGRAMS A1-A15, AEN, nBE0-nBE1 valid ...
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... FIGURE 15 - ADDRESS LATCHING FOR ALL MODES PARAMETER t8 A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE1 Hold After nADS Rising t25 A4-A15, AEN to nLDEV Delay SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications t8 t9 A1-A15, AEN, nBE0-nBE1 t25 MIN TYP ...
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... Read – RD0-RD31 Hold after RA2-RA16 Change t52 Read – nROE enable to RD0-RD31 Valid t53 Read – nROE disable to RD0-RD31 Invalid t50 Read/Write – Cycle Time SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications t50 t50 t54 t35 t38 ...
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... The following is the list of potential SRAMs and suppliers for the LAN91C110 Rev B. These SRAMs meet all timing requirements for LAN91C110 Rev B. But any other SRAM that meets the specification will also work with the LAN91C110 Rev B. Min ≥ 3ns Max≤15ns Min≤25ns Max≤12ns Max≤8ns Min≤12ns Min≤12ns Min≤15ns ...
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... TXD0-TXD3, TXEN100 Delay from TX25 Rising t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications t27 t27 FIGURE 17 - MII INTERFACE Page 53 ...
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... Note 4: Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.78- 1.08 mm. Note 5: Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAX REMARK 1 ...
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... Figure 6 - INTERRUPT STRUCTURE 36 Typical Flow of Events for Transmit 49 Timing diagrams and SRAM Application Note SMSC DS – LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications CORRECTION Replaced block diagram. Changed the the RX OVRN bit to a Reserved bit. Renamed pin nARDY to active high ARDY ...