CS61584A-IQ3ZR Cirrus Logic Inc, CS61584A-IQ3ZR Datasheet - Page 36

• Manufacturer Part Number: CS61584A-IQ3ZR
• Description: Network Controller & Processor ICs IC 3.3V/5V Dul T1/E1 Line Intrfc Unit
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IQ3ZR

• Product: Framer
• Number Of Transceivers: 2
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 3.465 V, 5.25 V
• Supply Voltage (min): 3.135 V, 4.75 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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10.16 Exit1-IR State
This is a temporary state. While in this state, if J-
TMS is held high, a rising edge applied to J-TCK
causes the controller to enter the Update-IR state,
which terminates the scanning process. If J-TMS is
held low and a rising edge is applied to J-TCK, the
controller enters the Pause-IR state. The test data
register selected by the current instruction retains
its previous value and the instruction does not
change during this state.
10.17 Pause-IR State
The pause state allows the test controller to tempo-
rarily halt the shifting of data through the instruc-
tion register. The test data register selected by the
current instruction retains its previous value and
the instruction does not change during this state.
The controller remains in this state as long as J-
TMS is low. When J-TMS goes high and a rising
edge is applied to J-TCK, the controller moves to
the Exit2-IR state.
10.18 Exit2-IR State
This is a temporary state. While in this state, if J-
TMS is held high, a rising edge applied to J-TCK
causes the controller to enter the Update-IR state,
which terminates the scanning process. If J-TMS is
held low and a rising edge is applied to J-TCK, the
controller enters the Shift-IR state.
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DS261PP5
The test data register selected by the current in-
struction retains its previous value and the instruc-
tion does not change during this state.
10.19 Update-IR State
The instruction shifted into the instruction register
is latched into the parallel output from the shift-reg-
ister path on the falling edge of J-TCK. When the
new instruction has been latched, it becomes the
current instruction. The test data registers selected
by the current instruction retain their previous val-
ue.
10.20 JTAG Application Examples
Figures 25 and 26 illustrate examples of updating
the instruction and data registers during JTAG op-
eration.
CS61584A
CS61584A
DS261PP5
DS261F1