LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 171

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
BITS
5:0
8
7
6
Duplex Mode (VPHY_DUPLEX)
This bit is used to set the duplex when the
is disabled.
0: Half Duplex
1: Full Duplex
Collision Test (VPHY_COL_TEST)
This bit enables/disables the collision test mode. When set, the collision
signal to the external MAC is active during transmission from the external
MAC.
Note:
0: Collision test mode disabled
1: Collision test mode enabled
Speed Select MSB (VPHY_SPEED_SEL_MSB)
This bit is not used by the Virtual PHY and has no effect. The value returned
is always 0.
RESERVED
Note 13.17 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 13.18 The isolation does not apply to the MII management pins (MDIO).
It is recommended that this bit be used only when in loopback
mode.
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
DESCRIPTION
DATASHEET
Auto-Negotiation (VPHY_AN)
171
bit
TYPE
R/W
R/W
RO
RO
Revision 1.4 (07-07-10)
DEFAULT
0b
0b
0b
-