LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 40

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
4.2.3.3
4.2.4
4.2.4.1
(PHY_BASIC_CONTROL_x)
clear approximately 110uS after the Port 1 PHY reset occurrence.
Note: When using the Reset bit to reset the Port 1 PHY, register bits designated as NASR are not
Refer to
Virtual PHY Reset
A Virtual PHY reset is performed by setting the VPHY_RST bit of the
(RESET_CTL), VPHY_RST bit in the
the
affected by this reset.
Virtual PHY reset completion can be determined by polling the VPHY_RST bit in the
Register
or the Reset bit in the
normal conditions, the VPHY_RST and Reset bit will clear approximately 1uS after the Virtual PHY
reset occurrence.
Refer to
resets.
Configuration Straps
Configuration straps allow various features of the LAN9312 to be automatically configured to user
defined values. Configuration straps can be organized into two main categories: hard-straps and soft-
straps. Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST).
The primary difference between these strap types is that soft-strap default values can be overridden
by the EEPROM Loader, while hard-straps cannot.
Configuration straps which have a corresponding external pin include internal resistors in order to
prevent the signal from floating when unconnected. If a particular configuration strap is connected to
a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to
ensure that it reaches the required voltage level prior to latching. The internal resistor can also be
overridden by the addition of an external resistor.
Note: The system designer must guarantee that configuration strap pins meet the timing
Soft-Straps
Soft-strap values are latched on the release of POR or nRST and are overridden by values from the
EEPROM Loader (when an EEPROM is present). These straps are used as direct configuration values
or as defaults for CPU registers. Some, but not all, soft-straps have an associated pin. Those that do
not have an associated pin, have a tie off default value. All soft-strap values can be overridden by the
EEPROM Loader.
Straps which have an associated pin are also fully defined in
Configuration," on page
on the operation of the EEPROM Loader and the loading of strap values.
Upon setting the DIGITAL_RST bit in the
RELOAD command via the
original latched (non-overridden) values if an EEPROM is no longer attached or has been erased. The
associated pins are not re-sampled. (i.e. The value latched on the pin during the last POR or nRST
will be used, not the value on the pin during the digital reset or RELOAD command issuance). If it is
desired to re-latch the current configuration strap pin values, a POR or nRST must be issued.
Virtual PHY Basic Control Register
reset.
requirements specified in
If configuration strap pins are not at the correct voltage level prior to being latched, the
LAN9312 may capture incorrect strap values.
Section 7.2.10, "PHY Resets," on page 95
(RESET_CTL), the VPHY_RST bit in the
Section 7.3.2, "Virtual PHY Resets," on page 98
Table 4.2
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
26. Refer to
provides a list of all soft-straps and their associated pin or default value.
EEPROM Command Register
until it clears. Under normal conditions, the PHY1_RST and Reset bit will
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Section 15.5.2, "Reset and Configuration Strap Timing," on page
DATASHEET
Section 10.2.4, "EEPROM Loader," on page 149
Power Management Control Register
(VPHY_BASIC_CTRL). No other modules of the LAN9312 are
40
Reset Control Register (RESET_CTL)
Power Management Control Register
for additional information on Port 1 PHY resets.
for additional information on Virtual PHY
(E2P_CMD), these straps return to their
Chapter 3, "Pin Description and
(PMT_CTRL), or Reset in
Reset Control Register
until it clears. Under
or upon issuing a
for information
SMSC LAN9312
Reset Control
(PMT_CTRL),
Datasheet
443.