78Q2120C09-CGTR/F Maxim Integrated Products, 78Q2120C09-CGTR/F Datasheet
78Q2120C09-CGTR/F
Specifications of 78Q2120C09-CGTR/F
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78Q2120C09-CGTR/F Summary of contents
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DESCRIPTION The 78Q2120C is a 10BASE-T/100BASE-TX Fast Ethernet transceiver. It includes integrated MII, ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation function. The transmitter includes an on-chip pulse-shaper and a low-power line driver. The receiver has an adaptive equalizer and ...
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FUNCTIONAL DESCRIPTION GENERAL Power Management The 78Q2120C has three power saving modes: • Chip Power-Down • Receive Power Management • Transmit High Impedance Mode Chip power-down is activated by setting the PWRDN bit in MII register MR0.11 or pulling high ...
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CDR immediately re-aligns the phase of the clock to synchronize with the incoming data. Hence clock acquisition is fast and immediate. 100BASE-TX OPERATION 100BASE-TX Transmit The 78Q2120C contains all of the necessary circuitry to convert the transmit MII signaling from ...
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SQE TEST The 78Q2120C supports the Signal Quality Error (SQE) function detailed in IEEE-802.3. interval of 1µs after each negative transition of the TXEN pin in 10BASE-T mode, the COL pin will go high for a period of 1µs. SQE ...
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Station Management Interface The station management interface consists of circuitry which implements the serial protocol as described in Clause 22.2.4.5 of IEEE-802.3. A 16- bit shift register receives serial data applied to the MDIO pin at the rising-edge of the ...
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PIN DESCRIPTION LEGEND TYPE DESCRIPTION A Analog Pin CIU TTL-level Input w/ Pull-up (5V compatible) CID TTL-level Input w/ Pull-down (5V compatible) CIS TTL-level Input w/ Schmitt Trigger (5V compatible) CO CMOS Output MII (MEDIA INDEPENDENT INTERFACE) NAME PIN TYPE ...
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MII (continued) NAME PIN TYPE 25 COZ RX_ER MDC 18 CIS MDIO 17 CIO PHY ADDRESS NAME PIN TYPE PHYAD[4:0] 12-16 CI PMA (PHYSICAL MEDIA ATTACHMENT) INTERFACE NAME PIN TYPE PCSBP 64 CID CONTROL AND STATUS NAME PIN TYPE 6 ...
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CONTROL AND STATUS (CONTINUED) NAME PIN TYPE ISO 2 CI ISODEF 1 CI ANEGA 47 CI TECH[2:0] 44-46 CI RPTR 50 CID MDI (MEDIA DEPENDENT INTERFACE) NAME PIN TYPE TXOP/N 61,62 A RXIP/N 52,51 A Page DESCRIPTION ...
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LED INDICATORS The LED pins use standard logic drivers. They output a logic low when the LED is meant and a logic high when it is meant to be off. The LED should be connected in series ...
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REGISTER DESCRIPTION The 78Q2120C implements 11 16-bit registers, which are accessible via the MDIO and MDC pins. The supported registers are shown below in the following table. Attempts to read unsupported registers will be ignored and the MDIO pin will ...
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MR0: Control Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 0.15 RESET R/SC 0.14 LOOPBK R/W 0.13 SPEEDSL R/W 0.12 ANEGEN R/W 0.11 PWRDN R/W 0.10 ISO R/W 0.9 RANEG R/SC Page Reset: Setting this bit to ‘1’ ...
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MR0: Control Register (continued) BIT SYMBOL TYPE DEFAULT DESCRIPTION 0.8 DUPLEX R/W 0.7 COLT R/W 0.6:0 RSVD R MR1: Status Register Bits 1.15 through 1.11 reflect the ability of the 78Q2120C as configured by the TECH[2:0] pins. They do not ...
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MR1: Status Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 1.9 100T2_H R 1.8 EXTS R 1.7 RSVD R 1.6 MFPS R 1.5 ANEGC R 1.4 RFAULT RC 1.3 ANEGA R 1.2 LINK R 1.1 JAB RC 1.0 EXTD R MR2: PHY ...
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MR4: Auto-Negotiation Advertisement Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 4. 4.14 RSVD R 4.13 RF R/W 4.12:5 TAF R/W (0Fh) 4. 4.11 A6 R/W 4.10 A5 R/W 4 4.8 A3 R/W 4.7 A2 R/W ...
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MR5: Auto-Negotiation Link Partner Ability Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 5. 5.14 ACK R 5. 5.12:5 A7:0 R 5.4:0 S4:0 R MR6: Auto-Negotiation Expansion Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 6.15:5 RSVD R 6.4 PDF ...
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MR16: Vendor Specific Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 16.15 RPTR R/W 16.14 INPOL R/W 16.13 RSVD R 16.12 TXHIM R/W 16.11 SQEI R/W 16.10 NL10 R/W 16.9 RSVD R/W 16.8 RSVD R/W 16.7 RSVD R/W 16.6 RSVD R/W 16.5 ...
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MR16: Vendor Specific Register (continued) Bit Symbol Type Default 16.1 PCSBP R/W 16.0 RXCC R/W MR17: Interrupt Control/Status Register The Interrupt Control/Status Register provides the means for controlling and observing events which trigger an interrupt on the INTR pin. This ...
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MR17: Interrupt Control/Status Register (continued) BIT SYMBOL TYPE DEFAULT DESCRIPTION 17.3 LP-ACK_INT RC 17.2 LS_CHG_INT RC 17.1 RFAULT_INT RC 17.0 ANEG- RC COMP_INT MR18: Diagnostic Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 18.15:13 RSVD R 18.12 ANEGF RC 18.11 DPLX R ...
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MR19: Transceiver Control BIT SYMBOL TYPE DEFAULT DESCRIPTION 19.15:12 RSVD R 19.11:10 TXO[1:0] R/W 19.9:0 RSVD R MR20: Reserved BIT SYMBOL TYPE DEFAULT DESCRIPTION 20.15:0 Reserved na MR21: Reserved BIT SYMBOL TYPE DEFAULT DESCRIPTION 21.15:0 Reserved na MR22: Reserved BIT ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation above maximum rating may permanently damage the device. PARAMETER DC Supply Voltage (Vcc) Storage Temperature Pin Voltage (CMOS inputs) Pin Voltage (CMOS outputs except TXOP/N) Pin Voltage (TXOP/N only) Pin Current RECOMMENDED OPERATING CONDITIONS ...
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DIGITAL I/O CHARACTERISTICS: Pins of type CI, CIU, CID, CIO: PARAMETER Input Voltage Low Input Voltage High Input Current Pull-up Resistance Pull-down Resistance Input Capacitance Pins of type CIS: PARAMETER Low-to-High Threshold High-to-Low Threshold Input Current Input Capacitance Pins of ...
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DIGITAL TIMING CHARACTERISTICS RST Characteristics VCC Oscillator RST PARAMETER SYMBOL RST Pulse Assertion Page reset RST Pulse Duration CONDITIONS Treset VCC = 3.3V and oscillator stabilized © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver MIN NOM ...
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MII Transmit Interface CHARACTERISTICS SYMBOL Setup Time: TX_CLK to TXD[3:0], TX_EN, TX_ER Hold Time: TX_CLK to TXD[3:0], TX_EN, TX_ER CKIN-to-TX_CLK Delay TX_CLK Duty-Cycle MII Receive Interface CHARACTERISTICS SYMBOL Receive Output Delay: RX_CLK to RXD[3:0], RX_DV, RX_ER RX_CLK Duty-Cycle RX_CLK RXD[3:0] ...
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MDIO Interface Input Timing CHARACTERISTICS SYMBOL Setup Time: MDC to MDIO Hold Time: MDC to MDIO Max Frequency: MDC MDIO Interface Output Timing CHARACTERISTICS SYMBOL MDC to MDIO data delay MDIO output from high Z to MCZ2D driven after MDC ...
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MDIO Interface Output Timing Page © 2009 Teridian Semiconductor Corporation 78Q2120C 10/100BASE-TX Transceiver Rev 1.3 ...
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System Timing System timing requirements for 100BASE-TX operation are listed in Table 24-2 of Clause 24 of IEEE 802.3. PARAMETER TX_EN Sampled to first bit of “J” on MDI output First bit of “J” on MDI input to CRS ...
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ANALOG ELECTRICAL CHARACTERISTICS 100BASE-TX Transmitter PARAMETER Peak Output Amplitude (|Vp+|, |Vp-|) (see note below) Output Amplitude Symmetry Output Overshoot Rise/Fall time (tr, tf) Rise/Fall time Imbalance Duty Cycle Distortion Jitter Note: Measured at the line side of the transformer. Test ...
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Receiver PARAMETER Signal Detect Assertion Threshold Signal Detect De-assertion Threshold Differential Input Resistance Jitter Tolerance (pk-pk) Baseline Wander Tracking Signal Detect Assertion Time Signal Detect De-assertion Time 10BASE-T Transmitter The Manchester-encoded data pulses, the link pulse and the start-of-idle ...
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Transmitter (Informative) The specifications in the following table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. PARAMETER Output return loss Output Impedance Balance Peak Common-mode Output Voltage ...
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... R4 R5 TLA-6T103 R16 49.9 49.9 TDK SMT16 R17 R18 0603 0603 75 75 C11 VCC 0.01 1.5KV C6 C5 1808 0.1 0.01 Note 2: This application circuit is only valid for the 78Q2120C09 revision. Refer to Ordering Information for revision identification. 78Q2120C RJ45 CGND Rev 1.3 ...
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ISOLATION TRANSFORMERS Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common- mode choke are recommended for exceeding FCC requirements. transformer characteristics: NAME Turns Ratio Open-Circuit Inductance Leakage Inductance Inter-Winding Capacitance D.C. Resistance Insertion Loss ...
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EXTERNAL CKIN OSCILLATOR CHARACTERISTICS PARAMETER SYMBOL CKIN Frequency f CKIN Period Tclkper CKIN Duty Cycle Rise / Fall Time Tr, Tf Absolute Jitter Note 1: IEEE 802.3 frequency tolerance ±50 ppm Page CKIN ...
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PACKAGE PIN DESIGNATIONS (Top View) ISODEF ISO GND CKIN GND RST PWRDN ...
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MECHANICAL SPECIFICATIONS 64-LQFP (Top View) 11.7 (0.460) 12.3 (0.484) PIN No. 1 Indicator 0.60 (0.024) Typ. Page 11.7 (0.460) 12.3 (0.484) 9.8 (0.386) 10.2 (0.402) 0.14 (0.006) 0.50 (0.0197) Typ. 0.28 (0.011) © 2009 Teridian Semiconductor Corporation ...
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... Teridian Semiconductor Corporation, 6440 Oak Canyon Rd. Suite 100, Irvine, CA 92618 (714) 508-8800, FAX: (714) 508-8877, http://www.teridiansemiconductor.com Page ORDER NUMBER 78Q2120C09-64CGT 78Q2120C09-64CGT/F Comments Final Data Sheet release 1. Revised ordering number (added 64) Changed CKIN table title 2. ...