78Q2120-64CG ETC [List of Unclassifed Manufacturers], 78Q2120-64CG Datasheet
78Q2120-64CG
Related parts for 78Q2120-64CG
78Q2120-64CG Summary of contents
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... DESCRIPTION The 78Q2120 is a 10BASE-T/100BASE-TX Fast Ethernet transceiver. It includes integrated MII, ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured functions. The transmitter includes an on-chip pulse- shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. ...
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... The 78Q2120 uses the reference clock and an external resistor to generate accurate bias voltages for the chip. CLOCK SELECTION The 78Q2120 will default to use the on-chip crystal oscillator. In this mode a 25MHz crystal is connected between the XTLP and XTLN pins. The CKIN pin should be tied low ...
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... The amount of gain and equalization applied to the pulses varies with the detected attenuation and dispersion and, therefore, with the length of the cable. The 78Q2120 can recover 10dB of loss in signal amplitude at 16 MHz. This loss is represented as test- chan 5 in AnnexA of the ANSI X3.263:199X specification and corresponds to approximately 140m of Cat5 UTP cabling ...
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... The natural loopback function can be enabled through register bit MR16.10. REPEATER MODE When the RPTR pin is high or register bit MR 16.15 is set the 78Q2120 is placed in repeater mode. In this mode, full duplex operation is prohibited, CRS responds only to receive activity and, in 10BASE-T mode, the SQE test function is disabled. ...
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... GENERAL PURPOSE I/O INTERFACE the station (80-TQFP ONLY) The 78Q2120 80-pin TQFP has a two pin, bi- directional, general purpose interface that can be used for external control or to monitor external signals. The direction of these pins and data that is either driven or read from these pins is configured via bits MR16 ...
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... TX_EN is high. In PCS bypass mode this pin becomes the higher-order bit of the transmit 5-bit code group. OZ CARRIER SENSE: When the 78Q2120 is not in repeater mode, CRS is high whenever a non-idle condition exists on either the transmitter or the receiver. In repeater mode, CRS is only active when a non-idle condition exists on the receiver ...
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... The same power-down state can also be achieved through the PWRDN bit in the MII register (MR0.11). I ISOLATE: When set to logic one, the 78Q2120 will present a high impedance on its MII output pins. This allows for multiple chips to be attached to the same MII interface. When the 78Q2120 is isolated, it still responds to management impedance state can also be achieved through the ISO bit in the MII register (MR0 ...
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... Ethernet Transceiver CONTROL AND STATUS (continued) PIN 64-PIN 80-PIN ANEGA 47 56 TECH[2:0] 44-46 53-55 RPTR 50 61 MDI (MEDIA DEPENDENT INTERFACE) TXOP, 61, 62 77,78 TXON RXIP, 52, 51 64,63 RXIN LED INDICATORS The LED pins use standard logic drivers. They output a logic low when the LED is meant and a logic high when it is meant to be off ...
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... BIAS CURRENT SETTING RESISTOR tied to an external resistor which is also connected to pin 70. This resistor should be placed as close as possible to the package pin. See Figure 1 for suggested value. A BIAS CURRENT SETTING RESISTOR RETURN PIN connected to external RIBB resistor. 9 78Q2120 10/100BASE-TX Ethernet Transceiver 0.5V, or ...
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... Ethernet Transceiver REGISTER DESCRIPTION The 78Q2120 implements ten 16-bit registers which are accessible via the MDIO and MDC pins. The supported registers are shown below. Unsupported registers will be read as all zeros. All of the registers respond to the broadcast address, PHYAD value 00000. ...
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... A logic one indicates 100BASE-TX operation and a logic zero indicates 10BASE-T. When auto-negotiation is enabled, this bit will have no effect on the 78Q2120. At reset, this bit reflects the highest operating speed allowed by the TECH [2:0] pins. The MII can write to this bit, but the bit will change value only if the new value is allowed by the TECH [2:0] pins ...
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... SYMBOL 0.8 DUPLEX R, W, (1) 0.7 COLT 0.6:0 RSVD MR1 - STATUS REGISTER Bits 1.15 through 1.11 reflect the ability of the 78Q2120 as configured by the TECH[2:0] pins They do not reflect any ability changes made via the MII management interface to bits 0.13 (SPEEDSL), 0.12 (ANEGEN) and 0.8 (DUPLEX). BIT SYMBOL 1.15 100T4 1.14 100X_F 1.13 100X_H 1 ...
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... C0-39 for TDK Semiconductor Corporation. This translates to a value of 300h for this register. ORGANIZATIONALLY UNIQUE IDENTIFIER: Remaining 6 bits of the OUI. MODEL NUMBER: The last 2 digits of the model number 78Q2120 is encoded into the 6 bits. (20d = 14h) R REVISION NUMBER: For example, a value of 0010 corresponds to the second version of the silicon. TYPE ...
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... R, 0 NEXT PAGE ABLE: Permanently tied to logic zero since the 78Q2120 does not support next page function PAGE RECEIVED: Set when a properly matched link code word has been received into the Auto-negotiation Link Partner. ...
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... GPIO0 pin as an input. Resetting it configures GPIO0 as an output. (80-pin TQFP only AUTO POLARITY: During auto-negotiation and 10BASE-T mode, the 78Q2120 is able to automatically invert the received signal - both the Manchester data and link pulses - if necessary. Setting this bit disables this feature. R, (W), 0 ...
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... Ethernet Transceiver MR16 - VENDOR SPECIFIC REGISTER (continued) BIT SYMBOL 16.1 PCSBP 16.0 RXCC MR17 - INTERRUPT CONTROL/STATUS REGISTER The Interrupt Control/Status Register provides the means for controlling and observing the events which trigger an interrupt on the INTR pin. This register can also be used in a polling mode via the MII serial interface as a means to observe key events within the PHY via one register address ...
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... RECEIVE LOCK: Indicates that the receive PLL has locked onto the received signal for the selected speed of operation (10BASE-T or 100BASE-TX). This bit is cleared whenever a cycle-slip occurs, and will remain cleared until it is read. RESERVED. Must be zero. 17 78Q2120 10/100BASE-TX Ethernet Transceiver been detected (but not ...
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... Ethernet Transceiver ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation above maximum rating may permanently damage the device. PARAMETER DC Supply Voltage Storage Temperature Pin Voltage Pin Current RECOMMENDED OPERATING CONDITIONS Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges: ...
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... V 5. 4.0mA OH V 4. 4.0mA OL T 4. 4.0mA 3. 2.0mA OH V 3. 2.0mA OL T 3. 2.0mA 78Q2120 10/100BASE-TX Ethernet Transceiver MIN NOM MAX 0.8 2.0 -10 + -0 -0.4 CC 0.4 5 UNIT ...
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... TX_CLK Duty-Cycle MII RECEIVE INTERFACE CHARACTERISTICS Receive Output Delay: RX_CLK to RXD[3:0], RX_DV, RX_ER RX_CLK Duty-Cycle (continued) TRANSMIT INPUTS TO THE 78Q2120 SYMBOL CONDITIONS CKIN RECEIVE OUTPUTS FROM THE 78Q2120 SYMBOL CONDITIONS RX DLY 20 MIN NOM MAX UNIT MIN ...
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... Hold Time: MDC to MDIO Max Frequency: MDC MDIO INTERFACE OUTPUT TIMING CHARACTERISTICS MDC to MDIO data delay MDIO output from high Z to driven after MDC MDIO output from driven to high Z after MDC MDIO AS AN INPUT TO THE 78Q2120 SYMBOL CONDITIONS MIO SU MIO HD F max ...
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... Ethernet Transceiver ELECTRICAL SPECIFICATIONS MDIO INTERFACE OUTPUT TIMING (continued) 22 ...
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... Jabber off-time* * Guarantee by design. The specifications in the above table are not tested during production test. They are included for information only. CONDITION input to CRS input to COL RPTR = low RPTR = low CONDITION 23 78Q2120 10/100BASE-TX Ethernet Transceiver NOM UNIT ...
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... Ethernet Transceiver ELECTRICAL SPECIFICATIONS (continued) ANALOG ELECTRICAL CHARACTERISTICS 100BASE-TX Transmitter PARAMETER *Peak Output Amplitude, Vp+, Vp- Output Amplitude Symmetry Output Overshoot Rise/Fall time, tr, tf Rise/Fall time Imbalance Duty Cycle Distortion 100BASE-TX Transmitter The specifications in the following table are not tested during production test. They are included for information only. ...
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... Link Pulse Width Start-of-Idle Pulse Width ** Measured at the line side of the transformer. Test Conditions: Transformer p/n: TLA-6T103 Line Termination: 100 RIBB: 9.76K ±1% @3.3V CONDITION CONDITION All data patterns ±1% 25 78Q2120 10/100BASE-TX Ethernet Transceiver MIN NOM MAX UNIT 600 900 1000 300 ...
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... Ethernet Transceiver 10BASE-T Transmitter The specifications in the following table are not tested during production test. They are included for information only. Output return loss Harmonic Content Output Impedance Balance Peak Common-mode Output Voltage Common-mode rejection Common-mode rejection jitter 10BASE-T Receiver ...
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... Ethernet Transceiver 27 78Q2120 ...
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... Ethernet Transceiver 28 ...
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... Vrms VALUE 25.00000 Parallel Resonance, Fundamental Mode > below main within 500 kHz 29 78Q2120 10/100BASE-TX Ethernet Transceiver This table gives the CONDITION @ 10 mV, 10 kHz @ 1 MHz (min 100 MHz For the transmit line UNITS MHz pF PPM PPM/yr ...
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... Ethernet Transceiver MECHANICAL SPECIFICATIONS 64-QFP 64-TQFP 30 ...
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... LQFP) 10/100BASE-TX Ethernet Transceiver 31 78Q2120 ...
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... Ethernet Transceiver PACKAGE PIN DESIGNATIONS (Top View) 64-Lead TQFP (JEDEC LQFP) and 64 QFP 32 CAUTION: Use handling procedures necessary for a static sensitive component ...
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... TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877 TDK Semiconductor Corporation 80-LEAD TQFP (JEDEC LQFP) ORDER NUMBER 78Q2120-CGT 78Q2120-64CG 78Q2120-64T 33 78Q2120 10/100BASE-TX Ethernet Transceiver CAUTION: Use handling procedures necessary for a static sensitive component PACKAGE MARK 78Q2120-CGT 78Q2120-64CG 78Q2120-64T 04/20/00- rev. I ...