LAN88710BMR SMSC, LAN88710BMR Datasheet - Page 43

• Manufacturer Part Number: LAN88710BMR
• Description: Ethernet ICs MII/RMII 10/100 Automot Transceiver
• Manufacturer: SMSC

Specifications of LAN88710BMR

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: QFN-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Footprint MII/RMII 10/100 Ethernet Transceiver for Automotive Applications
Datasheet
SMSC LAN88710AM/LAN88710BM
3.8.3.2
3.8.4
3.8.5
3.8.5.1
3.8.5.2
Energy Detect Power-Down
This power-down mode is activated by setting the
Register. In this mode, when no energy is present on the line the transceiver is powered down (except
for the management interface, the SQUELCH circuit, and the ENERGYON logic). The ENERGYON
logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-T, or Auto-negotiation
signals.
In this mode, when the
powered-down and nothing is transmitted. When energy is received via link pulses or packets, the
ENERGYON
state prior to power-down and asserts the nINT interrupt if the ENERGYON interrupt is enabled in the
Interrupt Mask
When the
disabled.
Isolate Mode
The device data paths may be electrically isolated from the MII/RMII interface by setting the
of the
TXEN and TXER inputs, but does respond to management transactions.
Isolation provides a means for multiple transceivers to be connected to the same MII/RMII interface
without contention. By default, the transceiver is not isolated (on power-up (Isolate=0).
Resets
The device provides two forms of reset: hardware and software. The device registers are reset by both
hardware and software resets. Select register bits, indicated as “NASR” in the register definitions, are
not cleared by a software reset. The registers are not reset by the power-down modes described in
Section
Note: For the first 16 µs after coming out of reset, the MII/RMII interface will run at 2.5 MHz. After
Hardware Reset
A hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held
low for the minimum time detailed in
on page 72
supplied to the XTAL1/CLKIN signal.
Note: A hardware reset (nRST assertion) is required following power-up. Refer to
Software Reset
A Software reset is activated by setting the
registers bits, except those indicated as “NASR” in the register definitions, are cleared by a Software
reset. The
reset process will be completed within 0.5 s from the setting of this bit.
Basic Control Register
this time, it will switch to 25 MHz if auto-negotiation is enabled.
"Power-On nRST & Configuration Strap Timing," on page 72
3.8.3.
EDPWRDOWN
Soft Reset
to ensure a proper transceiver reset. During a hardware reset, an external clock must be
bit goes high and the transceiver powers-up. The device automatically resets into the
Register. The first and possibly the second packet to activate ENERGYON may be lost.
bit is self-clearing. Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the
ENERGYON
bit of the
to “1”. In isolation mode, the transceiver does not respond to the TXD,
DATASHEET
Mode Control/Status Register
bit of the
Section 5.6.3, "Power-On nRST & Configuration Strap Timing,"
43
Soft Reset
Mode Control/Status Register
EDPWRDOWN
bit of the
is low, energy detect power-down is
Basic Control Register
for additional information.
bit of the
is low, the transceiver is
Mode Control/Status
Revision 1.1 (05-26-10)
Section 5.6.3,
to “1”. All
Isolate
bit