CS8900A-CQ3 Cirrus Logic Inc, CS8900A-CQ3 Datasheet - Page 73

• Manufacturer Part Number: CS8900A-CQ3
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQ3

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
Failure to observe these three rules may
cause data corruption.
4.8.1 Transferring Odd-Byte-Aligned Data
Some applications gather transmit data from
more than one section of host memory. The
boundary between the various memory loca-
tions may be either even- or odd-byte aligned.
When such a boundary is odd-byte aligned,
the host should transfer the last byte of the first
block to an even address, followed by the first
byte of the second block to the following odd
address. It can then resume word transfers.
An example of this is shown in Figure 17.
4.8.2 Random Access to CS8900A Mem-
ory
The first 118 bytes of a receive frame held in
the CS8900A’s on-chip memory may be ran-
domly accessed in Memory mode. After the
first 118 bytes, only sequential access of re-
ceived data is allowed. Either byte or word ac-
cess is permitted, as long as all word accesses
are executed to even-byte boundaries.
CS8900A
Crystal LAN™ Ethernet Controller
byte address must be followed by a byte
access to an odd-byte address before the
host may execute a word access (this will
realign the word transfers to even-byte
boundaries). On the other hand, a byte ac-
cess to an odd-byte address may be fol-
lowed by a word access.
Figure 17. Odd-Byte Aligned Data
Word Transfer
Word Transfer
Word Transfer
Word Transfer
Word Transfer
Word Transfer
Byte Transfer
Byte Transfer
First Block of Data
Second Block of Data
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4.9 Memory Mode Operation
To configure the CS8900A for Memory Mode,
the PacketPage memory must be mapped into
a contiguous 4-kbyte block of host memory.
The block must start at an X000h boundary,
with the PacketPage base address mapped to
X000h. When the CS8900A comes out of re-
set, its default configuration is I/O Mode. Once
Memory Mode is selected (by setting the
Memory E bit (BusCTL Register)), all of the
CS8900A’s registers can be accessed directly.
In Memory Mode, the CS8900A supports
Standard or Ready Bus cycles without intro-
ducing additional wait states.
Memory moves can use MOVD (double-word
transfers) as long as the CS8900A’s memory
base address is on a double word boundary.
Since 286 processors don’t support the MOVD
instruction, word and byte transfers must be
used with a 286.
4.9.1 Accesses in Memory Mode
The CS8900A allows Read/Write access to
the internal PacketPage memory, and Read
access of the optional Boot PROM. (See
Section 3.7 on page 27 for a description of the
optional Boot PROM.)
A memory access occurs when all of the fol-
lowing are true:
Description Mnemonic Read/Write
Transmit
Receive
Receive
Receive
Length
Frame
Frame
Status
Table 17. Receive/Transmit Memory Locations
RxLength
RxFrame
RxStatus
TxFrame
Read-only
Read-only
Read-only starts at 0404h
Write-only starts at 0A00h
0400h-0401h
0402h-0403h
PocketPage
Location:
base +
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