CS61584A-IQ5 Cirrus Logic Inc, CS61584A-IQ5 Datasheet - Page 29

• Manufacturer Part Number: CS61584A-IQ5
• Description: Network Controller & Processor ICs IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IQ5

• Product: Framer
• Number Of Transceivers: 2
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 3.465 V, 5.25 V
• Supply Voltage (min): 3.135 V, 4.75 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

tude information written for phases 13 and 14 of
each UI is ignored. Examples of arbitrary wave-
forms are illustrated in Figure 19.
The amplitude of each phase segment is described
by a 7-bit, 2’s complement number (bit 8 is ig-
nored). A positive value describes pulse amplitude
and a negative value describes pulse undershoot.
For DSX-1 applications with CON[3:0] = 1010, the
typical output voltage step is 73 mV/LSB across
the secondary (line side) of the transformer. For
DS1 applications with CON[3:0] = 1011, the typi-
cal output voltage step is 52 mV/LSB across the
transformer secondary. For E1 75
cations with CON[3:0] = 1000, the typical output
voltage step is 43 mV/LSB. For E1 120
pair applications with CON[3:0] = 1001, the typi-
cal output voltage step is 52 mV/LSB.
DS261PP5
DS261F1
Figure 19. Phase Definition of Arbitrary Waveforms
E1 Arbitrary Waveform Example
DSX-1 (54% duty cycle) Arbitrary Waveform Example
DS-1 (50% duty cycle) Arbitrary Waveform Example
coaxial appli-
twisted-
DS261PP5
The full scale positive value is 0x3F and the full
scale negative value is 0x40. It is recommended
that the output voltage across the secondary of the
transformer (line interface side) be limited to
4.4 Vpk. At higher output voltages, the transmitter
may not be able to drive the requested voltage
based on the current operating conditions.
Because the transmitter drives either a mark or a
space to the line interface every UI, the phase am-
plitude information defined in UI2 and UI3 is add-
ed to the symbols transmitted at TTIP and TRING
in those intervals. Therefore, a mark defined only
for UI1 will be output exactly as programmed if an-
other mark is transmitted in the next two UI. How-
ever, a mark defined over UI1 and UI2 with an
extended return-to-zero "tail" will cause the lead-
ing edge of a mark transmitted in the next UI to rise
or fall more quickly. This is illustrated in Figure 20.
If the hexadecimal sum of the phase amplitudes ex-
ceeds the full scale values, the sum is replaced by
the full scale value and the Latched-Overflow bit is
set in the Status register.
Figure 20. Example of Summing of Waveforms
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