MT88L89AN1 Zarlink, MT88L89AN1 Datasheet

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MT88L89AN1

Manufacturer Part Number
MT88L89AN1
Description
DTMF TXRX 3.58MHz CMOS 3V 24-Pin SSOP Tube
Manufacturer
Zarlink
Datasheet

Specifications of MT88L89AN1

Package
24SSOP
Operating Frequency
3.58 MHz
Typical Supply Current
3.1 mA
Typical Operating Supply Voltage
3 V
Minimum Operating Supply Voltage
2.7 V
Maximum Operating Supply Voltage
3.6 V
Features
Applications
Description
The MT88L89 is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
TONE
Complete DTMF transmitter/receiver
Low voltage operation (2.7-3.6 V)
Pin for pin compatible with existing MT8880,
MT8888 and MT8889 devices
Adaptive micro interface enables compatibility
with Intel and Motorola processors
DTMF transmitter/receiver power-down via
register control
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30 dBm
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Pay phones
Remote monitor/Control systems
OSC1
OSC2
IN+
GS
IN-
V
+
-
DD
Oscillator
Circuit
Circuit
V
Bias
Gating Cct.
Tone Burst
Ref
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Tone
Filter
Dial
V
SS
Copyright 1999-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Converters
High Group
Low Group
D/A
Control
Filter
Filter
Logic
Control
Logic
Figure 1 - Functional Block Diagram
Zarlink Semiconductor Inc.
ESt
Counters
Row and
Column
and Code
Converter
Algorithm
Digital
Steering
Logic
St/GT
1
3 V Integrated DTMF Transceiver with
The receiver section is based upon the industry
standard MT8870 DTMF receiver. The transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT88L89 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external logic.
The
features.
independently be powered down via register control.
Transmit Data
MT88L89AE
MT88L89AN
MT88L89AP
MT88L89AS
MT88L89ANR1 24 Pin SSOP* Tubes
MT88L89AS1
MT88L89ANR
MT88L89ASR
MT88L89ASR1 20 Pin SOIC*
Receive Data
MT88L89
Register
Register
Register
Register
Status
Control
Register
Control
The
A
B
Ordering Information
Adaptive Micro Interface
*Pb Free Matte Tin
provides
transmitter
-40°C to +85°C
20 Pin PDIP
24 Pin SSOP
28 Pin PLCC
20 Pin SOIC
20 Pin SOIC*
24 Pin SSOP
20 Pin SOIC
enhanced
Buffer
Control
Data
Interrupt
Bus
Logic
I/O
and
Tubes
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tape & Reel
receiver
Data Sheet
MT88L89
power-down
September 2005
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
may

Related parts for MT88L89AN1

MT88L89AN1 Summary of contents

Page 1

... Oscillator Circuit OSC2 Bias Circuit Ref SS Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2005, Zarlink Semiconductor Inc. All Rights Reserved Integrated DTMF Transceiver with MT88L89AE MT88L89AN MT88L89AP MT88L89AS MT88L89ANR1 24 Pin SSOP* Tubes MT88L89AS1 MT88L89ANR MT88L89ASR MT88L89ASR1 20 Pin SOIC* The receiver section is based upon the industry standard MT8870 DTMF receiver ...

Page 2

... See Figure 10. MT88L89 IN VDD 2 23 IN- St/ ESt GS 21 VRef VSS D2 19 OSC1 OSC2 TONE 15 10 IRQ/CP R/W/ DS/ RS0 24 PIN SSOP Figure 2 - Pin Connections Description /2 Zarlink Semiconductor Inc. Data Sheet • VRef VSS 7 23 OSC1 OSC2 PIN PLCC . SS ...

Page 3

... MT88L89 Description frees the device to accept a new tone pair. TSt generator. In addition, the IRQ, TONE output and DATA pins are held in Ref /2. Provision is made for connection of a feedback resistor to the op Zarlink Semiconductor Inc. Data Sheet TSt ...

Page 4

... DTMF signals. VOLTAGE GAIN ( DIFFERENTIAL INPUT AMPLIFIER (R2R5)/(R2 + R5) FOR UNITY GAIN R5=R1 MT88L89 MT88L89 IN+ IN Ref Figure 3 - Single-Ended Input Configuration C1 MT88L89 IN IN Ref VOLTAGE GAIN (A diff) = R5/R1 V INPUT IMPEDANCE 2 (Z diff (1/ωC) IN Figure 4 - Differential Input Configuration 4 Zarlink Semiconductor Inc. Data Sheet 2 ...

Page 5

... D D HIGH 3 2 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 * 1 0 1477 # 1 1 1633 1633 1633 1633 LOGIC LOW, 1= LOGIC HIGH ), v reaches the threshold ( the steering logic to register the tone c GTP TSt 5 Zarlink Semiconductor Inc. Data Sheet ...

Page 6

... GTA Figure 6 - Guard Time Adjustment ≥ REC DPmax GTPmax DAmin ≤ REC DPmin GTPmin DAmax ≥ DAmax GTAmax DPmin ≤ DAmin GTAmin DPmax 6 Zarlink Semiconductor Inc. Data Sheet ) TSt - TSt - TSt / TSt t t < ) GTP GTA - TSt / TSt t > ) GTP GTA ...

Page 7

... A t REC V in ESt St/GT RX -RX DECODED TONE # (n- Read Status Register IRQ/CP MT88L89 REC ID TONE TONE # GTP t GTA t PStRX # n t PStb3 Figure 7 - Receiver Timing Diagram 7 Zarlink Semiconductor Inc. Data Sheet is the minimum signal duration REC with a long t REC TONE # TSt # ( GTP DO ...

Page 8

... Hz. Typically, the high group to low group amplitude ratio (twist compensate for high group attenuation on long loops. MT88L89 Figure 8 - Description of Timing Events LOW 8 Zarlink Semiconductor Inc. Data Sheet and f ) are referred to as Low Group HIGH ...

Page 9

... Figure 9 shows that the distortion products are very low in amplitude. MT88L89 Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz Figure 9 - Spectrum Plot -25 0 250 500 FREQUENCY (Hz) = Reject = May Accept = Accept Figure 10 - Call Progress Response 9 Zarlink Semiconductor Inc. Data Sheet 750 ...

Page 10

... MT88L89 Output Frequency (Hz) Specified Actual L1 697 699.1 L2 770 766.2 L3 852 847.4 L4 941 948.0 H1 1209 1215.9 H2 1336 1331.7 H3 1477 1471.9 H4 1633 1645 fundamental Equation 1. THD (%) For a Single Tone 10 Zarlink Semiconductor Inc. Data Sheet %Error +0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 +0. .... V nf ...

Page 11

... V as measured on the output waveform. The total the sum of all the intermodulation components. The IMD .... + IMD Equation 2. THD (%) For a Dual Tone MT88L89 OSC1 OSC2 OSC1 OSC2 Figure 11 - Common Crystal Connection 11 Zarlink Semiconductor Inc. Data Sheet and V correspond to the low group MT88L89 ...

Page 12

... The IRQ/CP pin is an open drain output and requires an external pull-up resistor (see Figure 13 and Figure 14). MT88L89 8xL5x MT88L89 CS A8-A15 D0-D3 ALE RS0 P0 DS/RD RD R/W/ Zarlink Semiconductor Inc. Data Sheet MT88L89 CS D0-D3 RS0 DS/RD R/W/WR 12 (b) Intel ...

Page 13

... Write to Transmit Data Register 1 0 Read from Receive Data Register 0 1 Write to Control Register 1 0 Read from Status Register IRQ CP/DTMF TOUT Table 4 - CRA Bit Positions S/D RxEN BURST ENABLE Table 5 - CRB Bit Positions Description 13 Zarlink Semiconductor Inc. Data Sheet ...

Page 14

... Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal. Table 8 - Status Register Description 14 Zarlink Semiconductor Inc. Data Sheet Status Flag Cleared Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode. ...

Page 15

... Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT88L89 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. 15 Zarlink Semiconductor Inc. Data Sheet ...

Page 16

... Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT88L89 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. 16 Zarlink Semiconductor Inc. Data Sheet ...

Page 17

... NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms ( MT88L89 Initialization Procedure Motorola Intel RS0 R RS0 R Figure 15 - Application Notes 17 Zarlink Semiconductor Inc. Data Sheet Data ± 2 ms) AFTER THE DATA IS ± ...

Page 18

... I 2.0 DDQ 3.0 I 2.0 DDTX I 3.0 DDRX I 3 0.7 V IHO DD V ILO V 0.43 0.46 0.51 V TSt Zarlink Semiconductor Inc. Data Sheet Min. Max. 5 -0 -65 +150 1000 Max. Units Test Conditions 3.6 V °C +85 3.583124 MHz Max. Units Test Conditions µA 15.0 Vdd = 2 ...

Page 19

... OLE I 0.7 9 OLI ) unless otherwise stated ‡ Sym. Min. Typ. Max. I 100 PSRR 50 CMRR VOL fc 0 100 LGS R 50 LGS 19 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions V No load V No load µ load kΩ Note µ µ =0. =0. =0.9V ...

Page 20

... Voltages are with respect to ground (V ‡ Sym. Min. Typ. f 320 540 HR -30 20 Zarlink Semiconductor Inc. Data Sheet = 25° Units Test Conditions Load pp DD Note 9 ) unless otherwise stated. SS Units Notes* dBm 1,2,3,5,6,13 mV 1,2,3,5,6 RMS ...

Page 21

... RWS t 26 RWH DHR t 125 DDR 21 Zarlink Semiconductor Inc. Data Sheet Units Conditions ms Note 11 ms Note 11 µs Figure 7, Note 9 µs Figure 7, Note 9 ms DTMF mode ms DTMF mode ms Call Progress mode ms Call Progress mode dBm R =10kΩ LT dBm R =10kΩ ...

Page 22

... Figure 16 - Digital Signal Input Rise/Fall Times MT88L89 - Voltages are with respect to ground (V ‡ Sym. Min. Typ DSW t 10 DHW t 45 CSS t 10 CSH RDS, DSS ± 1. ± 2%) ≥ 1000 Zarlink Semiconductor Inc. Data Sheet ), unless otherwise stated. SS Max. Units Conditions ns Figures 17 Figures 17 Figures Figures Figures 17 ...

Page 23

... DSS R/W t Read AD3-AD0 (RS0, D0-D3) Write AD3-AD0 (RS0-D0-D3) Addr * non-mux AS.Addr * microprocessor pins Figure 17 - Motorola BUS Timing Diagram MT88L89 RWS t DDR AS Addr Addr CSH High Byte of Addr t CSS 23 Zarlink Semiconductor Inc. Data Sheet t RWH t DHR Data Data t t DSW DHW ...

Page 24

... RD must be high on the falling edge of CS for Intel Bus Timing MT88L89 t CSS DDR AH Data A8-A15 Address t CSH Figure 18 - Intel Read Timing Diagram t CSS DSW t AH Data A8-A15 Address t CSH Figure 19 - Intel Write Timing Diagram 24 Zarlink Semiconductor Inc. Data Sheet t DHR DHW ...

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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...

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