MT8967AS1 Zarlink, MT8967AS1 Datasheet
MT8967AS1
Specifications of MT8967AS1
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MT8967AS1 Summary of contents
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... Integrated PCM Filter Codec MT8960/61/64/65AE MT8962/63AE MT8962/63/66/67AS MT8963/66ASR MT8960/64/65AE1 MT8961AE1 MT8962ASR1 MT8962/63AE1 MT8962/66AS1 MT8963AS1 MT8963ASR1 MT8967AS1 MT8966/67ASR1 Description Manufactured in filter/codecs are designed to meet the demanding performance needs of the digital telecommunications industry, e.g., PABX, Central Office, Digital telephones. Analog to Digital PCM Encoder A Register ...
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... CSTi 18 GNDD DSTi 17 VRef C2i 16 GNDA DSTo 15 VR VDD 14 ANUL SD5 13 VX SD4 12 VEE F1i 11 SD0 CA 10 SD1 SD3 Figure 2 - Pin Connections Description 2 Zarlink Semiconductor Inc. Data Sheet MT8962/63/66/ GNDD 2 19 VRef 18 3 GNDA ANUL VEE 13 8 SD0 12 9 SD1 11 SD2 ...
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... Analog Input Voltage (V Bit 7... 0 MSB LSB Figure 3 - µ-Law Encoder Transfer Characteristic 3 Zarlink Semiconductor Inc. Data Sheet MT8964/66 Digital Output 10000000 10001111 10011111 10101111 10111111 11001111 11011111 11101111 11111111 01111111 01101111 ...
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... PCM word, fed back from the codec and MT8960/61/62/63/64/65/66/67 -2.5V -1.25V 0V +1.25V Analog Input Voltage ( Zarlink Semiconductor Inc. Data Sheet MT8965/67 Digital Output 10101010 10100101 10110101 10000101 10010101 11100101 11110101 11000101 ...
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... IN X pin which provides the reference voltage for the digital encoding Ref = 2.5 V, the digital encode decision value for overload (maximum Ref = 2.415 V (µ-Law version) or 2.5 V (A-Law version) and defined as ± OFFSET ± V C=0 OFFSET 5 Zarlink Semiconductor Inc. Data Sheet ...
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... This capacitor should have good high frequency Ref Figure 5 - Typical Voltage Reference Circuit the eighth clock pulse causing DSTo to enter high impedance and , in order to enter an 8-bit control word into Register B. In this case Zarlink Semiconductor Inc. Data Sheet V Ref 0.1 µF MT8960-67 FILTER/CODEC ) the EE ...
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... CSTi enters Register A. For Mode 3, F1i must logic low for two periods of 3.9 µs, in each 125 µs cycle. In the first period, CA must be at GNDD or V period CA must be high (V . DD) MT8960/61/62/63/64/65/66/67 ) which is used to control the function of the filter/codec. It operates Zarlink Semiconductor Inc. Data Sheet is connected to GNDA R , and in the second EE ...
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... Eight-bit control word into Register A. Register B is reset. Eight-bit control word into register A. Register B is unaffected. Eight-bit control word into register A. Register B is unaffected. TRANSMIT (A/D) BIT 1 BIT 0 FILTER GAIN (dB RECEIVE (D/A) BIT 4 BIT 3 FILTER GAIN (dB Zarlink Semiconductor Inc. Data Sheet . DD ...
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... MT8960/61/62/63/64/65/66/67 TRANSMIT (A/D) BIT 1 BIT 0 FILTER GAIN (dB) BIT 6 FUNCTION CONTROL 0 Normal operation 1 Digital Loopback 0 Analog Loopback 1 Powerdown Table 2 - Control States - Register A input and the output in each case Zarlink Semiconductor Inc. Data Sheet ) the chip CC output. (See Table 3 for not tested by this R ...
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... PCM Highway Protection MT8960/61 Battery MT8962/63 Feed 2W/4W MT8964/65 Converter Ringing MT8966/67 Figure 6 - Typical Line Termination LOGIC CONTROL OUTPUTS LOGIC CONTROL OUTPUT SD LOGIC CONTROL OUTPUTS SD CHIP TESTING CONTROLS 10 Zarlink Semiconductor Inc. Data Sheet ) in Register B causes the SD outputs to and may be used control ...
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... LOGIC CONTROL OUTPUTS SD input X R input Table 3 - Control States - Register B and V causes powerdown for a period of 25 clock cycles and DD EE and CSTi held at continuous logic high the chip assumes the same state as 11 Zarlink Semiconductor Inc. Data Sheet - GNDD. Power is EE will be connected R ...
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... EE SD3 SD0 SD2 SD1 Figure 7 - Typical Use of the Special Drive Outputs 0.1µF Ring Trip Gain Filter Section (With Relay Drive) 12 Zarlink Semiconductor Inc. Data Sheet Message Waiting -100 V DC (With Relay Drive) 2/4 Wire Telephone Converter Line Ring Feed - - (With Relay ...
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... Repeated for Lines 2 to 255 8 8 DSTi V X DSTo V R CDTi SD0 . . • • . • SDn MT8960-67 13 Zarlink Semiconductor Inc. Data Sheet Line Interface & Circuitry Line 1 • • • Repeated for Lines 2 to 255 Line Interface & Monitoring Circuitry Line 256 ...
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... EE V 2.5 Ref VGNDD -0.1 0.0 +0.1 -0.4 0 3.0 4 3.0 4 2.0 Ref I 0.25 1.0 DDO I 0.25 1.0 EEO ° Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.3 +6.0 V -6.0 +0.3 V GNDA GNDD-0 -0 GNDD-0 ...
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... OUT C 4.0 OUT +1.0 OSIN R 100 OUT V 100 OSO UT 5V supplies. For design aid only: not guaranteed and not subject to production testing. 15 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions µ GNDD µ +1 µA Output High Impedance µ ...
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... ISH DSTi t 0 ISL CSTi DSTi PCS supplies. For design aid only: not guaranteed and not subject to production testing. 16 Zarlink Semiconductor Inc. Data Sheet Max Units Test Conditions 2.05 MHz See Note 100 ns 100 ns ns See Note 4 ns See Note 4 100 ns ...
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... D QX2 35.30 29.30 24. SFX 150 250 17 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions Level at codec: µ-Law: 3.17 dBm0 A-Law: 3.14 dBm0 PP See Note 6 +0. dBm0 @ 1004 Hz +0.35 dB from nominal, @ 1004 =0°C to 70°C A ...
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... PSS R 2 (See ± 5V supplies. For design aid only: not guaranteed and not subject to production testing µ -Law codec. 18 Zarlink Semiconductor Inc. Data Sheet Sinusoidal Input Level -30 dBm0 dB -40 dBm0 dB -45 dBm0 -55 dB 50/ -23 dBm0 and any signal within 300-3400 dBm0 ...
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... D QR2 36.40 30.40 25. SFR IMD R2 IMD R3 IMD R4 19 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions Level at codec: µ-Law: 3.17 dBm0 A-Law: 3.14 dBm0 pp R =10 KΩ L See Note 7 +0. dBm0 1004Hz @ +0.35 dB From nominal, ...
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... CT TR PSRR 33 3 PSRR supplies. For design aid only: not guaranteed and not subject to production testing. for A-Law codec. RMS 20 Zarlink Semiconductor Inc. Data Sheet µs 210 @ 1004 Hz µs Input Signal: µs 400 - 3200 Hz digital µs sinewave at 0 dBm0 0.125 dB 0 dBm0 Input Signal ...
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... MT8960/61/62/63/64/65/66/67 C2i INPUT F1i INTERNAL ENABLE DSTo OUTPUT DSTi INPUT (Mode CSTi INPUT LOAD A-REGISTER LOAD B-REGISTER Figure 9a - Timing Diagram - 125 µs Frame Period 125 µs HIGH IMPEDANCE Zarlink Semiconductor Inc. Data Sheet ...
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... C2i. EH 90% C2i 50% Input 10% 90% DSTo 50% Output 10% t PLH 90% DSTi, CSTi 50% Input 10% t MT8960/61/62/63/64/65/66/67 8 CLOCK CYCLES (See Note PZL t PZH Figure 9b - Timing Diagram - Output Enable PLH ISH Figure 9c - Timing Diagram - Input/Output 22 Zarlink Semiconductor Inc. Data Sheet ISL high-Z and ES ...
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... Figure 10 - Attenuation vs Frequency for Transmit (A/D) Filter SCALE A SCALE B -0.125 0.125 0. 3000 3200 3300 3400 FREQUENCY (Hz) 23 Zarlink Semiconductor Inc. Data Sheet STOPBAND ATTENUATION ∏(4000-F) SIN - 1200 ∏(4000-F) -18 SIN -7/9 1200 Note: Above function crossover occurs at 4000Hz. 4000 4600 5000 10000 ...
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... Attenuation Relative To Attenuation At 1 kHz (dB 100 200 Figure 11 - Attenuation vs Frequency for Receive (D/A) Filter SCALE A -0.125 0.125 0. 300 3000 3200 3300 3400 FREQUENCY (Hz) 24 Zarlink Semiconductor Inc. Data Sheet SCALE B STOPBAND ATTENUATION -14 SIN ∏(4000-F) 1200 4000 4600 5000 10000 - 1 ...
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... Sinusoidal Test Signal Figure 12 - Variation of Gain With Input Level +1.0 +0.5 +0.25 0 -30 -20 -10 -0.25 -0.5 -1.0 CCITT End-To-End Spec -40 -30 -20 -10 25 Zarlink Semiconductor Inc. Data Sheet 1 Channel Spec 2 Input Level (dBm0) - Sinusiodal Test Signal 1 Channel Spec 2 Input Level (dBm0 ...
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... Figure 13 - Signal to Total Distortion Ratio vs Input Level 35.6 33.9 33.9 32.2 27.6 -20 -34 -30 -27 Input Level (dBm0) 36.4 35.3 33.0 -30 -20 Input Level (dBm0) 26 Zarlink Semiconductor Inc. Data Sheet 1 Channel Spec 2 28.0 26.3 CCITT End-To-End Spec - Channel Spec 36.4 2 D/A ...
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... MT8960/61/62/63/64/65/66/67 1000 750 500 370 (600Hz) 250 125 0 500 1000 Figure 14 - Envelope Delay Variation Frequency 1500 2000 27 Zarlink Semiconductor Inc. Data Sheet CCITT ½ Channel Spec (2800Hz) (2600Hz) 2500 3000 ...
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... MT8960/61/62/63/64/65/66/ *Relative to Fundamental Output power level with +3 dBm0 input signal level at a frequency of 1.02 kHz. Figure 15 - Overload Distortion (End-to-End Input Level (dBm0) 28 Zarlink Semiconductor Inc. Data Sheet 8 9 ...
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