LE58QL021BVC Zarlink, LE58QL021BVC Datasheet - Page 11

• Manufacturer Part Number: LE58QL021BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

DRA, DRB
DXA, DXB
FS
INT
MCLK/E1
PCLK
RST
TSCA, TSCB
VCCA, VCCD
VIN
VOUT
VOUT
VREF
Pin Names
1
–VIN
1
4
–
4
Inputs
Outputs
Input
Output
Input/Output
Input
Input
Outputs
Power
Inputs
Outputs
Output
Type
PCM Data Receive A/B. The PCM data for channels 1, 2, 3, and 4 is serially received on either
the DRA or DRB port during user-programmed time slots. Data is always received with the
most significant bit first. For compressed signals, 1 byte of data for each channel is received
every 125 µs at the PCLK rate. In the Linear state, two consecutive bytes of data for each
channel are received every 125 µs at the PCLK rate. DRB is not available on all package
types.
PCM Data Transmit. The transmit data from channels 1, 2, 3, and 4 is sent serially out on
either the DXA or DXB port or both ports during user-programmed time slots. Data is always
transmitted with the most significant bit first. The output is available every 125 µs and the data
is shifted out in 8-bit (16-bit in Linear or PCM Signaling state) bursts at the PCLK rate. DXA
and DXB are High impedance between time slots, while the device is in the Inactive state with
no PCM signaling, or while the Cutoff Transmit Path bit (CTP) is on. DXB is not available on
all package types.
Frame Sync. The Frame Sync pulse is an 8 kHz signal that identifies Time Slot 0, Clock Slot
0 of a system’s PCM frame. The QLSLAC device references individual time slots with respect
to this input, which must be synchronized to PCLK.
Interrupt. INT is an active Low output signal which is programmable as either TTL compatible
or open drain. The INT output goes Low any time one of the input bits in the Real Time Data
register changes state and is not masked. It also goes Low any time new transmit data
appears if this interrupt is armed. INT remains Low until the appropriate register is read via
the microprocessor interface, or the QLSLAC device receives either a software or hardware
reset. The individual CD
interrupt by using MPI Command 6C/6Dh. The transmit data interrupt must be armed with a
bit in the Operating Conditions register.
Master Clock (Input)/Enable CD1 Multiplex (Output). The Master Clock can be a 1.536 MHz,
1.544 MHz, or 2.048 MHz (times 1, 2, or 4) clock for use by the digital signal processor. If the
internal clock is derived from the PCM Clock Input (PCLK), this pin can be used as an E1
output to control Legerity SLIC devices having multiplexed hookswitch and ground-key
detector outputs.
PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or
out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum
clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz for dual PCM
highway versions and 256 kHz for single PCM highway versions. The minimum clock rate
must be doubled if Linear state or PCM signaling is used. PCLK frequencies between 1.03
MHz and 1.53 MHz are not allowed. Optionally, the digital signal processor clock can be
derived from PCLK rather than MCLK.
Reset. A logic Low signal at this pin resets the QLSLAC device to its default state. The RST
pin may be tied to VCCD if it is not needed in the system.
Time Slot Control. The Time Slot Control outputs are open drain outputs (requiring pull-up
resistors to VCCD) and are normally inactive (High impedance). TSCA or TSCB is active
(Low) when PCM data is transmitted on the DXA or DXB pin respectively.
Analog and digital power supply inputs. VCCA and VCCD are provided to allow for noise
isolation and proper power supply decoupling techniques. For best performance, all of the
VCC power supply pins should be connected together at the connector of the printed circuit
board.
Analog Input. The analog voice band signal is applied to the VIN input of the QLSLAC device.
The VIN input is biased at VREF by a large internal resistor. The audio signal is sampled,
digitally processed and encoded, and then made available at the TTL-compatible PCM output
(DXA or DXB). If the digitizer saturates in the positive or negative direction, VIN is pulled by a
reduced resistance toward AGND or VCCD, respectively. VIN
is the input for channel 2, VIN
Analog Output. The received digital data at DRA or DRB is processed and converted to an
analog signal at the VOUT pin. VOUT
channel 2, VOUT
VOUT voltages are referenced to VREF.
Analog Voltage Reference. The VREF output is provided in order for an external capacitor to be
connected from VREF to ground, filtering noise present on the internal voltage reference.
VREF is buffered before it is used by internal circuitry. The voltage on VREF and the output
resistance are given in
capacitor must be low.
Zarlink Semiconductor Inc.
3
is the output from channel 3, and VOUT
11
Electrical Characteristics, on page
xy
bits in the Real Time Data register can be masked from causing an
3
is the input for channel 3, and VIN
1
Description
is the output from channel 1, VOUT
13. The leakage current in the
4
1
is the output for channel 4. The
is the input for channel 1, VIN
4
is the input for channel 4.
2
is the output for
2