S19233PRIB AMCC, S19233PRIB Datasheet - Page 18

• Manufacturer Part Number: S19233PRIB
• Description: Ethernet/Fibre Channel 49-Pin BGA
• Manufacturer: AMCC

Specifications of S19233PRIB

• Package: 49BGA
• Maximum Data Rate: 11.32 Gbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 380 mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3.03 V
• Maximum Operating Supply Voltage: 1.95|3.56 V

S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Dual CDR
PIN ASSIGNMENTS AND DESCRIPTIONS
Table 9. Signals Pin Assignments and Descriptions
18
TXDATINP
TXDATINN
TXCAP1
TXCAP2
TXLOCK
TXDATOUTP
TXDATOUTN
RXDATINP
RXDATINN
RXCTAP
RXCAP1
RXCAP2
LOS_SD
RXDATOUTP
RXDATOUTN
RXLOCK
Pin Name
Diff CML
Diff CML
Diff CML
Diff CML
Analog
Analog
Analog
Pull-up
LVTTL
LVTTL
LVTTL
Speed
Speed
Speed
Speed
Level
3.3 V
3.3 V
3.3 V
High
High
High
High
I/O
I/O
O
O
O
O
I
I
I
I
I
Pin#
G7
G6
D7
C7
E6
A5
A6
A1
A2
C2
D1
E1
G3
G2
C4
F4
Transmit Serial Data Input. Differential high speed serial data input for
transmitter. Internally terminated 100 Ω line-to-line (50 Ω + 50 Ω with center
tap capacitor). This input must be AC coupled. Clock is recovered from tran-
sitions on these inputs.
Transmit Loop Filter Capacitors. Connections for external loop filter capaci-
tors and resistors. See Figure 14, External Loop Filters, and Table 19, Trans-
mit and Receive External Loop Filter Components.
Transmit Lock. Active High. Goes active after the transmit PLL has locked
on the incoming data stream after initially locking onto the clock provided on
the REFCLK pins. TXLOCK is an asynchronous output.
Transmit Serial Data Output. Serial data stream signals, normally con-
nected to an optical transmitter module. Output return loss, S
-12dB at 15 GHz.
Receive Serial Data Input. Differential high speed serial data input for
receiver. Internally biased and terminated 100 Ω line-to-line (50 Ω + 50 Ω
with center tap capacitor). This input must be AC coupled.
Center Tap Input. This input should be connected to a broadband 850 pF
capacitor to ground.
Receive Loop Filter Capacitors. Connections for external loop filter capac-
itors and resistors. See Figure 14, External Loop Filters, and Table 19,
Transmit and Receive External Loop Filter Components.
Dual purpose pin -
Loss of Signal Output for Receiver or Signal Detect Input for Receiver.
Active High. Goes active after the receiver fail to sense the incoming data
stream. This Loss of Signal is an asynchronous output.
When LOS_SD register is set to 0 via
Detect Input for Receiver.
Signal Detect Input for Receive. active HIGH default. May be adjusted to
be active low with
receiver module to indicate sufficient received optical power. When inactive
the RX PLL will be forced to lock to the REFCLKP/N inputs and the data will
be forced to a logical '0' or 1' state depending on the polarity of SQ_POL sig-
nal and squelch enable feature.
Serial data output for Receiver.
Receive Lock. Active High. Goes active after the receive PLL has locked on
the incoming data stream after initially locking onto the clock provided on the
REFCLK pins. RXLOCK is an asynchronous output.
TRANSMITTER SIGNALS
RECEIVER SIGNALS
I
2
C
control. Signal to be driven by the external optical
Description
I
2
C
Revision 5.00 – March 16, 2007
, this pin becomes the Signal
AMCC Confidential and Proprietary
Data Sheet
22
of