AD7722ASZ Analog Devices Inc, AD7722ASZ Datasheet - Page 21

• Manufacturer Part Number: AD7722ASZ
• Description: ADC Single Delta-Sigma 195KSPS 16-Bit Parallel/Serial 44-Pin MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD7722ASZ

• Package: 44MQFP
• Resolution: 16 Bit
• Sampling Rate: 195 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 1
• Digital Interface Type: Parallel|Serial (3-Wire)
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar|Bipolar
• Number Of Bits: 16
• Sampling Rate (per Second): 220k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 375mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To interface the AD7722 to other DSPs, the master clock
frequency of the AD7722 can be reduced so that the SCO
frequency equals the maximum allowable frequency of the serial
clock input to the DSP. When the AD7722 is operated with a
lower CLKIN frequency (< 10 MHz), DSPs, such as the
TMS320C20/C25 and DSP56000/1, can be used.
Figures 26 to 28 show the interfaces between the AD7722 and
several DSPs. In all cases, the interface control pins, TSI, DOE,
SFMT, CFMT, SYNC, and FSI, can be permanently hardwired
together to either DGND or DV
CFMT can be tied either high or low to configure the serial data
interface for the particular format required by the DSP. The
frame synchronization signal, FSI, can be applied from the user’s
system control logic.
REV. B
Figure 28. AD7722 to TMS320C20/TMS320C25/
TMS320C50 Interface
DOE (MASTER AND SLAVE)
Figure 26. AD7722 to ADSP-21xx Interface
AD7722
AD7722
Figure 27. AD7722 to DSP56000 Interface
AD7722
SDO (MASTER)
FSO (MASTER)
RESET/SYNC
SDO (SLAVE)
SDO
SCO
SDO
SCO
FSO
SDO
SCO
FSO
FSO
FSI (SLAVE)
NOTE 1:
THE STATE OF FSI CANNOT BE CHANGED
4 CLKIN CYCLES BEFORE A FSO EDGE.
CLKIN
SCO
FSI
DD
. Alternatively, SFMT or
D4
Figure 25. Timing for 2-Channel Multiplexed Operation
SC1
SRD
SCK
RFS
DR
SCLK
FSR
DR
CLKR
D3
DSP56001/2/3
t
t
TMS320Cxx
1
ADSP-21xx
14
D2
NOTE 1
D1
–21–
t
12
t
t
15
16
D0
Grounding and Layout
The analog and digital power supplies to the AD7722 are indepen-
dent and separately pinned out to minimize coupling between
analog and digital sections within the device. The AD7722 should
be treated as an analog component and grounded and decoupled
to the analog ground plane. All the AD7722 ground pins should
be soldered directly to a ground plane to minimize series induc-
tance. All converter power pins should be decoupled to the analog
ground plane. To achieve the best decoupling, place surface-
mount capacitors as close as possible to the device, ideally right
up against the device pins.
The printed circuit board that houses the AD7722 should use
separate ground planes for the analog and digital interface
circuitry. All converter power pins should be decoupled to the
analog ground plane, and all interface logic circuit power pins
should be decoupled to the digital ground plane. This facili-
tates the use of ground planes, which can physically separate
sensitive analog components from the noisy digital system.
Digital and analog ground planes should only be joined in one
place and should not overlap to minimize capacitive coupling
between them.
Separate power supplies for AV
desirable. The digital supply pin DV
a separate analog supply, but if necessary DV
power connection to AV
Figure 29). The 10 Ω resistor, in series with the DV
required to dampen the effects of the fast switching currents into
the digital section of the AD7722. The ferrite is also recommended
to filter high frequency signals from corrupting the analog
power supply.
A minimum etch technique is generally best for ground planes
because it gives the best shielding. Noise can be minimized by
paying attention to the system layout and preventing different
signals from interfering with each other. High level analog signals
should be separated from low level analog signals, and both should
be kept away from digital signals. In waveform sampling and
reconstruction systems, the sampling clock (CLKIN) is as vulner-
able to noise as any analog signal. CLKIN should be isolated from
D15
D14
DD
(see the connection diagram in
NOTE 1
D1
DD
and DV
t
11
t
t
DD
16
15
D0
should be powered from
DD
DD
are also highly
D15
AD7722
may share its
DD
pin, is