AD7722ASZ Analog Devices Inc, AD7722ASZ Datasheet - Page 5

• Manufacturer Part Number: AD7722ASZ
• Description: ADC Single Delta-Sigma 195KSPS 16-Bit Parallel/Serial 44-Pin MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD7722ASZ

• Package: 44MQFP
• Resolution: 16 Bit
• Sampling Rate: 195 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 1
• Digital Interface Type: Parallel|Serial (3-Wire)
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar|Bipolar
• Number Of Bits: 16
• Sampling Rate (per Second): 220k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 375mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Parameter
CLKIN Frequency
CLKIN Period (t
CLKIN Low Pulse Width
CLKIN High Pulse Width
CLKIN Rise Time
CLKIN Fall Time
FSI Low Time
FSI Setup Time
FSI Hold Time
CLKIN to SCO Delay
SCO Period
SCO Transition to FSO High Delay
SCO Transition to FSO Low Delay
SCO Transition to SDO Valid Delay
SCO Transition from FSI
SDO Enable Delay Time
SDO Disable Delay Time
DRDY High Time
Conversion Time
DRDY to CS Setup Time
CS to RD Setup Time
RD Pulse Width
Data Access Time after RD Falling Edge
Bus Relinquish Time after RD Rising Edge
CS to RD Hold Time
RD to DRDY High Time
SYNC/RESET Input Pulse Width
DVAL Low Delay from SYNC/RESET
SYNC/RESET Low Time after CLKIN Rising
DRDY High Delay after SYNC/RESET Low
DRDY Low Delay after SYNC/RESET Low
DVAL High Delay after SYNC/RESET Low
CAL Setup Time
CAL Pulse Width
NOTES
1
2
3
4
Specifications subject to change without notice.
REV. B
Guaranteed by design.
Frame sync is initiated on falling edge of CLKIN.
With RD synchronous to CLKIN, t
See Figure 8.
Calibration Delay from CAL High
Unipolar Input Calibration Time, (UNI = 0)
Bipolar Input Calibration Time, (UNI = 1)
Conversion Results Valid, (UNI = 0)
Conversion Results Valid, (UNI = 1)
1
CLK
1
= 1/f
2
CLK
22
)
can be reduced up to 1 t
(AV
1
1
f
CLKIN
3
DD
= 5 V
= 12.5 MHz, SFMT = Logic Low or High, CFMT = Logic Low or High.)
1
1
1, 4
1, 4
CLK
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5%, DV
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
34
35
36
37
37
38
38
.
DD
= 5 V
–5–
Min
0.3
0.067
0.45 × t
0.45 × t
5
5
2
20
20
2
2
64
0
0
t
0
10
10
10
1
CLK
+ 20
5%, AGND = DGND = 0 V, C
1
1
Typ
12.5
0.08
40
4
4
3
30
10
1
Max
15
3.33
0.55 × t
0.55 × t
10
10
8
2.5
45
30
t
t
40
t
50
(8192 + 64)
8192
2
64
(3 × 8192 + 2 × 512)
(4 × 8192 + 3 × 512)
(3 × 8192 + 2 × 512 + 64)
(4 × 8192 + 3 × 512 + 64)
CLK
CLK
CLK
L
= 50 pF, T
+ 40
+ 40
– 10
1
1
A
= T
MIN
to T
MAX
,
AD7722
Unit
MHz
µs
ns
ns
t
ns
ns
ns
t
ns
ns
ns
t
ns
ns
t
t
ns
ns
ns
ns
ns
ns
t
ns
ns
ns
ns
t
t
ns
t
t
t
t
t
t
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK