5962-8512702XA Analog Devices Inc, 5962-8512702XA Datasheet - Page 8

• Manufacturer Part Number: 5962-8512702XA
• Description: ADC Single SAR 12-Bit Parallel 28-Pin SBCDIP
• Manufacturer: Analog Devices Inc

Specifications of 5962-8512702XA

• Package: 28SBCDIP
• Resolution: 12 Bit
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar|Bipolar

AD574A
The full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 for a 10 V range). Trim R2 to
give the last transition (1111 1111 1110 to 1111 1111 1111).
BIPOLAR OPERATION
The connections for bipolar ranges are shown in Figure 5.
Again, as for the unipolar ranges, if the offset and gain specifica-
tions are sufficient, one or both of the trimmers shown can be
replaced by a 50
similar to unipolar calibration. First, a signal 1/2 LSB above
negative full scale (–4.9988 V for the 5 V range) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963 V the 5 V range) is applied and R2 trimmed to
give the last transition (1111 11111110 to 1111 1111 1111).
CONTROL LOGIC
The AD574A contains on-chip logic to provide conversion ini-
tiation and data read operations from signals commonly avail-
able in microprocessor systems. Figure 6 shows the internal
logic circuitry of the AD574A.
The control signals CE, CS, and R/C control the operation of
the converter. The state of R/C when CE and CS are both
asserted determines whether a data read (R/C = 1) or a convert
(R/C = 0) is in progress. The register control inputs A
12/8 control conversion length and data format. The A
usually tied to the least significant bit of the address bus. If a
conversion is started with A
is initiated. If A
conversion cycle results. During data read operations, A
mines whether the three-state buffers containing the 8 MSBs of
the conversion result (A
enabled. The 12/8 pin determines whether the output data is
to be organized as two 8-bit words (12/8 tied to DIGITAL
COMMON) or a single 12-bit word (12/8 tied to V
12/8 pin is not TTL-compatible and must be hard-wired to
either V
byte addressed when A
conversion followed by four trailing zeroes. This organization
allows the data lines to be overlapped for direct interface to
8-bit buses without the need for external three-state buffers.
It is not recommended that A
operation. Asymmetrical enable and disable times of the
three-state buffers could cause internal bus contention resulting
in potential damage to the AD574A.
LOGIC
Figure 5. Bipolar Input Connections
ANALOG
INPUTS
or DIGITAL COMMON. In the 8-bit mode, the
O
is high during a convert start, a shorter 8-bit
OFFSET
10V
5V
GAIN
1% fixed resistor. Bipolar calibration is
100
100
O
R2
R1
O
is high contains the 4 LSBs from the
= 0) or the 4 LSBs (A
O
low, a full 12-bit conversion cycle
O
10
12
13
14
2
3
4
5
6
8
9
change state during a data read
12/8
CS
A
R/C
CE
REF IN
REF OUT
BIP OFF
10V
20V
ANA COM
O
IN
IN
AD574A
DIG COM
MIDDLE
HIGH
BITS
LOW
BITS
+15V
–15V
STS
+5V
BIT
28
16
15
27
24
23
20
19
11
1
7
O
= 1) are
LOGIC
O
O
and
line is
O
). The
deter-
–8–
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
CE CS R/C 12/8
0
X
1
1
1
1
1
TIMING
The AD574A is easily interfaced to a wide variety of micropro-
cessors and other digital systems. The following discussion of
the timing requirements of the AD574A control signals should
provide the system designer with useful insight into the opera-
tion of the device.
Symbol
t
t
t
t
t
t
t
t
t
DSC
HEC
SSC
HSC
SRC
HRC
SAC
HAC
C
(NOTE 2)
STATUS
NOTE 1: WHEN START CONVERT GOES LOW, THE EOC (END OF CONVERSION) SIGNALS GO LOW.
NOTE 2: 12/8 IS NOT A TTL-COMPATABLE INPUT AND SHOULD ALWAYS BE WIRED DIRECTLY TO
12/8
X
1
0
0
0
0
0
Table II. Convert Start Timing—Full Control Mode
R/C
CE
CS
A0
EOC8 RETURNS HIGH AFTER AN 8-BIT CONVERSION CYCLE IS COMPLETE, AND EOC12
RETURNS HIGH WHEN ALL 12-BITS HAVE BEEN CONVERTED. THE EOC SIGNALS PREVENT
DATA FROM BEING READ DURING CONVERSIONS.
V
LOGIC
Parameter
STS Delay from CE
CE Pulse Width
CS to CE Setup
CS Low During CE High
R/C to CE Setup
R/C Low During CE High
A
A
Conversion Time
X
X
0
0
1
1
1
O
O
8-Bit Cycle
12-Bit Cycle
OR DIGITAL COMMON.
to CE Setup
Valid During CE High
Figure 6. AD574A Control Logic
X
X
X
X
Pin 1 X
Pin 15 0
Pin 15 1
Table I. AD574A Truth Table
CONVERT
READ
A
X
X
0
1
O
Operation
None
None
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
Enable 12-Bit Parallel Output
Enable 8 Most Significant Bits
Enable 4 LSBs + 4 Trailing Zeroes
LOW IF CONVERSION
IN PROGRESS
NIBBLE A, B,
ENABLE
NIBBLE C
ENABLE
NIBBLE B = O
ENABLE
Min
300
300
200
250
200
0
300
10
15
Typ Max
START CONVERT
VALUE OF A0
AT LAST CONVERT
COMMAND
EOC8
EOC12
TO OUTPUT
BUFFERS
400
24
35
NOTE 1
FROM
REV. B
Units
ns
ns
ns
ns
ns
ns
ns
ns
s
s