5962-8512702XA Analog Devices Inc, 5962-8512702XA Datasheet - Page 9

• Manufacturer Part Number: 5962-8512702XA
• Description: ADC Single SAR 12-Bit Parallel 28-Pin SBCDIP
• Manufacturer: Analog Devices Inc

Specifications of 5962-8512702XA

• Package: 28SBCDIP
• Resolution: 12 Bit
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar|Bipolar

REV. B
Figure 7 shows a complete timing diagram for the AD574A con-
vert start operation. R/C should be low before both CE and CS
are asserted; if R/C is high, a read operation will momentarily
occur, possibly resulting in system bus contention. Either CE or
CS may be used to initiate a conversion; however, use of CE is
recommended since it includes one less propagation delay than
CS and is the faster input. In Figure 7, CE is used to initiate the
conversion.
Once a conversion is started and the STS line goes high, convert
start commands will be ignored until the conversion cycle is
complete. The output data buffers cannot be enabled during
conversion.
Figure 8 shows the timing for data read operations. During data
read operations, access time is measured from the point where
CE and R/C both are high (assuming CS is already low). If CS
is used to enable the device, access time is extended by 100 ns.
In the 8-bit bus interface mode (12/8 input wired to DIGITAL
COMMON), the address bit, A
prior to CE going high and must remain stable during the entire
read cycle. If A
output buffers may result.
O
Figure 7. Convert Start Timing
Figure 8. Read Cycle Timing
is allowed to change, damage to the AD574A
O
, must be stable at least 150 ns
–9–
Symbol
t
t
t
t
t
t
t
t
t
NOTES
1
2
“STAND-ALONE” OPERATION
The AD574A can be used in a “stand-alone” mode, which is
useful in systems with dedicated input ports available and thus
not requiring full bus interface capability.
In this mode, CE and 12/8 are wired high, CS and A
low, and conversion is controlled by R/C. The three-state buff-
ers are enabled when R/C is high and a conversion starts when
R/C goes low. This allows two possible control signals—a high
pulse or a low pulse. Operation with a low pulse is shown in
Figure 11. In this case, the outputs are forced into the high
impedance state in response to the falling edge of R/C and return
DD
HD
HL
SSR
SRR
SAR
HSR
HRR
HAR
t
required for an output to cross 0.4 V or 2.4 V.
t
loaded with the circuit of Figure 10.
DD
HL
Figure 11. Low Pulse for R/ C —Outputs Enabled After
Conversion
2
1
is defined as the time required for the data lines to change 0.5 V when
is measured with the load circuit of Figure 9 and defined as the time
Figure 10. Load Circuit for Output Float Delay Test
a. High-Z to Logic 1
Figure 9. Load Circuit for Access Time Test
a. Logic 1 to High-Z
Table III. Read Timing—Full Control Mode
Parameter
Access Time (from CE)
Data Valid After CE Low
Output Float Delay
CS to CE Setup
R/C to CE Setup
A
CS Valid After CE Low
R/C High After CE Low
A
O
O
to CE Setup
Valid After CE Low
b. Logic 0 to High-Z
b. High-Z to Logic 0
Min Typ Max Units
25
150
0
150
50
0
50
AD574A
200
100
O
are wired
ns
ns
ns
ns
ns
ns
ns
ns
ns