MT47H32M16HR-3 IT:F TR Micron Technology Inc, MT47H32M16HR-3 IT:F TR Datasheet - Page 8

• Manufacturer Part Number: MT47H32M16HR-3 IT:F TR
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA T/R
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16HR-3 IT:F TR

• Density: 512 Mb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 250mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

List of Tables
Table 1: Key Timing Parameters ...................................................................................................................... 2
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 16
Table 4: Input Capacitance ............................................................................................................................ 20
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 21
Table 6: Temperature Limits .......................................................................................................................... 22
Table 7: Thermal Impedance ......................................................................................................................... 22
Table 8: General I
Table 9: I
Table 10: DDR2 I
Table 11: DDR2 I
Table 12: AC Operating Specifications and Conditions .................................................................................... 31
Table 13: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 42
Table 14: ODT DC Electrical Characteristics ................................................................................................... 43
Table 15: Input DC Logic Levels ..................................................................................................................... 44
Table 16: Input AC Logic Levels ..................................................................................................................... 44
Table 17: Differential Input Logic Levels ........................................................................................................ 45
Table 18: Differential AC Output Parameters .................................................................................................. 47
Table 19: Output DC Current Drive ................................................................................................................ 47
Table 20: Output Characteristics .................................................................................................................... 48
Table 21: Full Strength Pull-Down Current (mA) ............................................................................................ 49
Table 22: Full Strength Pull-Up Current (mA) ................................................................................................. 50
Table 23: Reduced Strength Pull-Down Current (mA) ..................................................................................... 51
Table 24: Reduced Strength Pull-Up Current (mA) .......................................................................................... 52
Table 25: Input Clamp Characteristics ........................................................................................................... 53
Table 26: Address and Control Balls ............................................................................................................... 54
Table 27: Clock, Data, Strobe, and Mask Balls ................................................................................................. 54
Table 28: AC Input Test Conditions ................................................................................................................ 55
Table 29: DDR2-400/533 Setup and Hold Time Derating Values (
Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (
Table 31: DDR2-400/533
Table 32: DDR2-667/800/1066
Table 33: Single-Ended DQS Slew Rate Derating Values Using
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 37: Truth Table – DDR2 Commands ..................................................................................................... 69
Table 38: Truth Table – Current State Bank n – Command to Bank n ............................................................... 70
Table 39: Truth Table – Current State Bank n – Command to Bank m .............................................................. 72
Table 40: Minimum Delay with Auto Precharge Enabled ................................................................................. 73
Table 41: Burst Definition .............................................................................................................................. 77
Table 42: READ Using Concurrent Auto Precharge ......................................................................................... 97
Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 103
Table 44: Truth Table – CKE ......................................................................................................................... 118
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
DD7
Timing Patterns (4-Bank Interleave READ Operation) ................................................................. 24
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Specifications and Conditions (Die Revision F) ................................................................ 25
Specifications and Conditions (Die Revision G) ................................................................ 28
Parameters .................................................................................................................... 24
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DH Derating Values with Differential Strobe ..................................................... 61
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DH Derating Values with Differential Strobe ............................................ 62
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
IS and
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and
REF
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512Mb: x4, x8, x16 DDR2 SDRAM
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) at DDR2-667 ..................................... 63
) at DDR2-533 ..................................... 64
) at DDR2-400 ..................................... 64
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DH
IH) ................................................... 57
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.................................................. 63
t
IH) .......................................... 58
© 2004 Micron Technology, Inc. All rights reserved.
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