72125L50SO Integrated Device Technology (Idt), 72125L50SO Datasheet

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72125L50SO

Manufacturer Part Number
72125L50SO
Description
FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 16 28-Pin SOIC
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 72125L50SO

Package
28SOIC
Configuration
Dual
Bus Directional
Uni-Directional
Density
16 Kb
Organization
1Kx16
Data Bus Width
16 Bit
Timing Type
Synchronous
Expansion Type
Depth|Width
Typical Operating Supply Voltage
5 V
Operating Temperature
-40 to 85 °C
FEATURES:
• 25ns parallel port access time, 35ns cycle time
• 45MHz serial output shift rate
• Wide x16 organization offering easy expansion
• Low power consumption (50mA typical)
• Least/Most Significant Bit first read selected by asserting
• Four memory status flags: Empty, Full, Half-Full, and
• Dual-Port zero fall-through architecture
• Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
• Industrial temperature range (–40 C to +85 C)
DESCRIPTION:
power,dedicated, parallel-to-serial FIFOs. These FIFOs
possess a 16-bit parallel input port and a serial output port with
256, 512 and 1,024 word depths, respectively.
FIFOs ideal for laser printers, FAX machines, local area
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
INDUSTRIAL TEMPERATURE RANGE
©1999 Integrated Device Technology, Inc.
the FL/DIR pin
Almost-Empty/Almost-Full
Integrated Device Technology, Inc.
The IDT72105/72115/72125s are very high-speed, low-
The ability to buffer wide word widths (x16) make these
RSOX
RSIX
/DIR
RESET
LOGIC
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
EXPANSION
LOGIC
POINTER
WRITE
CMOS PARALLEL-TO-SERIAL FIFO
256 x 16, 512 x 16, 1,024 x 16
SOCP
SERIAL OUTPUT
1,024 x 16
256 x 16
512 x 16
ARRAY
LOGIC
D
RAM
0–15
networks (LANs), video storage and disk/tape controller ap-
plications.
multiple chips. IDT’s unique serial expansion logic makes this
possible using a minimum of pins.
and one clock pin (SOCP). The Least Significant or Most
Significant Bit can be read first by programming the DIR pin
after a reset.
status flags: Empty, Full, Half-Full and Almost-Empty/Almost-
Full. The Full and Empty flags prevent any FIFO data overflow
or underflow conditions. The Half-Full Flag is available in both
single and expansion mode configurations. The Almost-
Empty/Almost-Full Flag is available only in a single device
mode.
leading edge, submicron CMOS technology. Military grade
product is manufactured in compliance with the latest revision
of Mil-STD-883, Class B.
16
Expansion in width and depth can be achieved using
The unique serial output port is driven by one data pin (SO)
Monitoring the FIFO is eased by the availability of four
The IDT72105/72115/72125 are fabricated using IDT’s
SO
POINTER
READ
LOGIC
FLAG
2665 drw 01
DECEMBER 1999
IDT72105
IDT72115
IDT72125
DSC-2665/-
1

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72125L50SO Summary of contents

Page 1

Integrated Device Technology, Inc. FEATURES: • 25ns parallel port access time, 35ns cycle time • 45MHz serial output shift rate • Wide x16 organization offering easy expansion • Low power consumption (50mA typical) • Least/Most Significant Bit first read selected ...

Page 2

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO 256 x 16, 512 x 16, 1,024 x 16 PIN CONFIGURATION PIN DESCRIPTIONS Symbol Name I/O D –D Inputs I Data inputs for 16-bit wide data Reset I When array. after power-up. only ...

Page 3

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO 256 x 16, 512 x 16, 1,024 x 16 STATUS FLAGS Number of Words in FIFO IDT72105 IDT72115 0 0 1–31 1–63 32–128 64–256 129–224 257–448 225–255 449–511 256 512 ABSOLUTE MAXIMUM RATINGS Symbol Rating V ...

Page 4

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO 256 x 16, 512 x 16, 1,024 ELECTRICAL CHARACTERISTICS (Industrial Symbol Parameter t Parallel Shift Frequency S t Serial Shift ...

Page 5

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO 256 x 16, 512 x 16, 1,024 TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load CAPACITANCE ( 1.0MHz) A ...

Page 6

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO 256 x 16, 512 x 16, 1,024 0–15 SOCP SO (First Device in Width Expansion Mode) (Single Device Mode or Second Device in Width Expansion Mode) SO NOTE Single Device Mode, ...

Page 7

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO 256 x 16, 512 x 16, 1,024 x 16 DATA IN NOTE 1 SOCP SO NOTES Once has gone LOW and the last bit of the final word has been shifted out, SOCP should ...

Page 8

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO 256 x 16, 512 x 16, 1,024 x 16 SOCP /DIR RSOX RSIX OPERATING CONFIGURATIONS Single Device Mode The device must be reset before beginning operation so that all flags are set to location zero. In ...

Page 9

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO 256 x 16, 512 x 16, 1,024 x 16 PARALLEL DATA IN LOW AT RESET D 0–15 SOCP FIFO #1 RSOX RSIX Depth Expansion (Daisy Chain) Mode The IDT72105/72115/72125 can easily be adapted to applications requiring ...

Page 10

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO 256 x 16, 512 x 16, 1,024 Mode Reset-First Device 0 Reset All Other Devices 0 Read/Write 1 NOTE Reset Input, /FIR ...

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