72125L50SO Integrated Device Technology (Idt), 72125L50SO Datasheet - Page 5

• Manufacturer Part Number: 72125L50SO
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 16 28-Pin SOIC
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72125L50SO

• Package: 28SOIC
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 16 Kb
• Organization: 1Kx16
• Data Bus Width: 16 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: -40 to 85 °C

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
AC TEST CONDITIONS
CAPACITANCE
NOTE:
1. Characterized values, not currently tested.
FUNCTIONAL DESCRIPTION
Parallel Data Input
that all flags are set to their initial state. In width or depth
expansion the First Load pin (
indicate the first device.
15
of the Write (
asserted. If the
Full Flag (
internally from incrementing the write pointer and no write
operation occurs.
rising edge of Write. On the rising edge of
NOTES:
1.
2.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
C
C
Symbol
input data lines. A write cycle is initiated on the falling edge
IN
OUT
SOCP
The device must be reset before beginning operation so
The data is written into the FIFO in parallel through the D
Data set-up and hold times must be met with respect to the
EF
SOCP should be in the steady LOW or HIGH during t
/DIR
,
,
,
FF
,
FF
HF
Input Capacitance
Output
Capacitance
) is already set, the write line is internally inhibited
and
W
Parameter
W
AEF
) signal provided the Full Flag (
signal changes from HIGH-to-LOW and the
may change status during Reset, but flags will be valid at t
(T
A
= +25 C, f = 1.0MHz)
(1)
FL
Conditions
V
) must be programmed to
V
OUT
IN
= 0V
= 0V
W
, the write pointer
See Figure A
GND to 3.0V
RSS
Max.
1.5V
1.5V
10
12
5ns
. The first LOW-HIGH (or HIGH-LOW) transition can begin after t
FF
) is not
2665 tbl 08
2665 tbl 07
t
Unit
RSS
Figure 1. Reset
pF
pF
0–
t
RSS
t
RS
is incremented. Write operations can occur simultaneously or
asynchronously with read operations.
Serial Data Output
out on the rising edge of SOCP providing the Empty Flag (
is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by SOCP.
Significant Bit first, depending on the
operation. A LOW on DIR will cause the Least Significant Bit
to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.
t
t
t
The serial data is output on the SO pin. The data is clocked
The serial word is shifted out Least Significant Bit or Most
RSC
RSC
RSC
RSC.
NOTE 2
OUTPUT
PIN
*Includes jig and scope capacitances.
TO
t
FLS
Figure A. Output Load
or equivalent circuit
680
INDUSTRIAL TEMPERATURE RANGE
5V
t
FLH
t
t
RSR
1.1K
RSR
RSR
30pF
FL
.
/DIR level during
*
2665 drw 03
2665 drw 04
FLAG
STABLE
FLAG
STABLE
5
EF
)