7200L30TDB Integrated Device Technology (Idt), 7200L30TDB Datasheet - Page 10

• Manufacturer Part Number: 7200L30TDB
• Description: FIFO Mem Async Dual Depth/Width Uni-Dir 256 x 9 28-Pin CDIP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 7200L30TDB

• Package: 28CDIP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 2.25 Kb
• Organization: 256x9
• Data Bus Width: 9 Bit
• Timing Type: Asynchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: -55 to 125 °C

USAGE MODES:
WIDTH EXPANSION
input control signals of multiple devices. Status flags (EF, FF and HF) can be
detected from any one device. Figure 13 demonstrates an 18-bit word width
by using two IDT7200/7201A/7202As. Any word width can be attained by
adding additional IDT7200/7201A/7202As (Figure 13).
BIDIRECTIONAL OPERATION
system capable of Read and Write operations) can be achieved by pairing
IDT7200/7201A/7202As as shown in Figure 16. Both Depth Expansion and
Width Expansion may be used in this mode.
DATA FLOW-THROUGH
and write flow-through mode. For the read flow-through mode (Figure 17),
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
Word width may be increased simply by connecting the corresponding
Applications which require data buffering between two systems (each
Two types of flow-through modes are permitted, a read flow-through
FULL FLAG (FF)
Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion Mode
DATA
RESET (RS)
WRITE (W)
FULL FLAG (FF)
IN
(D)
DATA IN (D)
RESET (RS)
WRITE (W)
18
(HALF-FULL FLAG)
Figure 12. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9 FIFO
EXPANSION IN (XI)
9
9
7201A/
7202A
7200/
IDT
HF
XI
7201A/
7202A
7200/
9
(HF)
IDT
10
9
the FIFO permits a reading of a single word after writing one word of data into
an empty FIFO. The data is enabled on the bus in (t
edge of W, called the first write edge, and it remains on the bus until the R line
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after t
deassertion and then would be asserted.
of a single word of data immediately after reading one word of data from a
full FIFO. The R line causes the FF to be deasserted but the W line being LOW
causes it to be asserted again in anticipation of a new data word. On the rising
edge of W, the new word is loaded in the FIFO. The W line must be toggled
when FF is not asserted to write new data in the FIFO and to increment the write
pointer.
COMPOUND EXPANSION
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
In the write flow-through mode (Figure 18), the FIFO permits the writing
The two expansion techniques described above can be applied together
7201A/
7202A
7200/
HF
IDT
9
RHZ
XI
ns. The EF line would have a pulse showing temporary
9
READ (R)
RETRANSMIT (RT)
DATA OUT (Q)
EMPTY FLAG (EF)
COMMERCIAL, INDUSTRIAL AND MILITARY
18
DATA
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
2679 drw 14
OUT
TEMPERATURE RANGES
2679 drw 15
(Q)
WEF
OCTOBER 22, 2008
+ t
A
) ns after the rising