IDT72255LA15PFG IDT, Integrated Device Technology Inc, IDT72255LA15PFG Datasheet
IDT72255LA15PFG
Specifications of IDT72255LA15PFG
800-1500
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IDT72255LA15PFG Summary of contents
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FEATURES • • • • • Choose among the following memory organizations: IDT72255LA — 8,192 x 18 IDT72265LA — 16,384 x 18 • • • • • Pin-compatible with the IDT72275/72285 SuperSync FIFOs • • • • • 10ns read/write ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 DESCRIPTION (CONTINUED) SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data. The input port is controlled ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 DESCRIPTION (CONTINUED) In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10 0°C to +70°C; Industrial: VCC = 5V ± 10 –40°C to +85°C) Symbol Parameter f Clock ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72255LA/72265LA support two different timing modes of operation: IDT Standard mode or First Word Fall ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72255LA/72265LA has internal registers for these offsets. Default set- tings are stated in the footnotes of ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 72255LA — 8,192 x 18–BIT 17 12 EMPTY OFFSET REGISTER DEFAULT VALUE 07FH LOW at Master Reset, 3FFH HIGH at Master Reset 17 ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combi- nation of ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing diagram. For either IDT Standard mode or FWFT mode, updating of the ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 SIGNAL DESCRIPTION INPUTS: DATA IN (D0 - D17) Data inputs for 18-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 that shifts the last word from the FIFO memory to the outputs. OR goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS If FWFT = HIGH, ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES JANUARY 13, 2009 ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES JANUARY 13, 2009 ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 RCLK t t ENS ENH t RTS REN WCLK t RTS WEN t ENS RT EF PAE HF PAF NOTES: ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 RCLK t t ENH ENS t RTS REN WCLK t RTS WEN t ENS RT OR PAE HF PAF NOTES: 1. Retransmit ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 WCLK Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) RCLK NOTE ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 CLKH CLKL WCLK t t ENH ENS ( words in FIFO (3) n+1 words in FIFO t SKEW2 RCLK 1 NOTES PAE ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. ...
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IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72255LA can easily be adapted to applications requiring depths greater than 8,192 and 16,384 for the IDT72265LA with an 18-bit bus width. ...
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ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device. 2. Green parts available. For specific speeds and packages contact your sales office. ...
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VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 DIFFERENCES BETWEEN THE IDT72255LA/72265LA AND IDT72255L/72265L IDT has improved the performance of the IDT72255/72265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is ...