IDT72285 Integrated Device Technology, IDT72285 Datasheet
IDT72285
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IDT72285 Summary of contents
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... FEATURES: • • • • • Choose among the following memory organizations: IDT72275 — 32,768 x 18 IDT72285 — 65,536 x 18 • • • • • Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs • • • • • 10ns read/write cycle time (6.5ns access time) • ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 DESCRIPTION (CONTINUED) SuperSync FIFOs are particularly appropriate for network, video, telecom- munications, data communications and other applications that need to buffer large amounts of data. The input port is ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 DESCRIPTION (CONTINUED) PAE and PAF can be programmed independently to switch at any point in memory. (See Table I and Table II.) Programmable offsets determine the flag switching threshold ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write ...
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... Input High Voltage (Com’l & Ind’l) 2.0 — Input Low Voltage (Com’l & Ind’l) — — Operating Temperature 0 — Commercial Operating Temperature -40 Industrial IDT72275 IDT72285 Commercial & Industrial ( 10, 15 CLK Min. Max. –1 1 –10 10 2.4 — — 0.4 — ...
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... GND to 3.0V 3ns 1.5V 1.5V See Figure 2 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Commercial & Industrial (2) IDT72275L15 IDT72275L20 IDT72285L15 IDT72285L20 Min. Max. Min. — 66.7 — — — — — — — ...
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... FIFO will cause the PAF to go LOW. Again reads are performed, the PAF will go LOW after (32,769-m) writes for the IDT72275 and (65,537-m) writes for the IDT72285, where m is the full offset value. The default setting for this value is stated in the footnote of Table 2. ...
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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FF PAF IDT72285 ( (2) to 65,535 H L 65,536 PAF IDT72285 ( ( 65,537 PAE ...
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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72285 (65,536 x 18 BIT EMPTY OFFSET REGISTER DEFAULT VALUE 007FH LOW at Master Reset, 03FFH HIGH at Master Reset 16 15 FULL OFFSET REGISTER DEFAULT VALUE 007FH LOW at Master Reset, ...
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... words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit setup 32,768 for the IDT72275 and D = 65,536 for the IDT72285. In FWFT mode 32,769 for the IDT72275 and D= 65,537 for the IDT72285. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS ...
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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 32,769 for the IDT72275 and 65,537 for the IDT72285) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information. ...
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... IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 (65,536-m) writes for the IDT72285. The offset “m” is the full offset value. The default setting for this value is stated in the footnote of Table 1. In FWFT mode, the PAF will go LOW after (32,769-m) writes for the IDT72275 and (65,537-m) writes for the IDT72285, where m is the full offset value ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS RSR t t RSS RSR ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS If FWFT = HIGH, ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 COMMERCIAL AND INDUSTRIAL 17 TEMPERATURE RANGES ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES ...
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... FIFO after Master Reset more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 32,768 for IDT72275 and 65,536 for IDT72285 goes HIGH RCLK cycle + t REF ...
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... OR goes LOW RCLK cycles + t REF WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72275 and for the IDT72285. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF t ...
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... PAF offset . maximum FIFO depth. In IDT Standard mode 32,768 for the IDT72275 and 65,536 for the IDT72285. In FWFT mode 32,769 for the IDT72275 and 65,537 for the IDT72285. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...
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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 32,768 for the IDT72275 and 65,536 for the IDT72285. 2. For FWFT mode maximum FIFO depth 32,769 for the IDT72275 and 65,537 for the IDT72285. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
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IDT72275/72285 CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. ...
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... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72275 can easily be adapted to applications requiring depths greater than 32,768 and 65,536 for the IDT72285 with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device. DATASHEET DOCUMENT HISTORY 04/24/2001 pgs and 25. 02/18/2003 pg. ...