IDT70V38L15PFI IDT [Integrated Device Technology], IDT70V38L15PFI Datasheet

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IDT70V38L15PFI

Manufacturer Part Number
IDT70V38L15PFI
Description
HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM
Manufacturer
IDT [Integrated Device Technology]
Datasheet
©2003 Integrated Device Technology, Inc.
Features
Functional Block Diagram
NOTES:
1. BUSY is an input as a Slave (M/S=V
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V38L
Dual chip enables allow for depth expansion without
external logic
IDT70V38 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
Active: 440mW (typ.)
Standby: 660µW (typ.)
I/O
BUSY
I/O
SEM
CE
CE
R/
INT
9-17L
A
OE
UB
LB
0-8L
A
15L
W
0L
0L
1L
L
L
L
L
L
L
L
(1,2)
(2)
IL
) and an output when it is a Master (M/S=V
Decoder
Address
R/W
CE
CE
OE
0L
1L
L
L
16
HIGH-SPEED 3.3V
64K x 18 DUAL-PORT
STATIC RAM
Control
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
64Kx18
ARRAY
70V38
LOGIC
M/S
IH
1
).
(1)
M/S = V
M/S = V
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Control
I/O
IL
IH
for BUSY input on Slave
for BUSY output flag on Master,
16
Address
Decoder
CE
CE
OE
R/W
0R
1R
R
R
SEPTEMBER 2003
4850 drw 01
IDT70V38L
R/
UB
CE
CE
OE
LB
BUSY
A
A
SEM
INT
I/O
I/O
15R
0R
W
R
R
0R
1R
R
R
R
9-17R
0-8R
R
(2)
R
(1,2)
DSC-4850/3
.

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IDT70V38L15PFI Summary of contents

Page 1

Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) Low-power operation – IDT70V38L Active: 440mW (typ.) Standby: 660µW (typ.) Dual chip enables allow for depth ...

Page 2

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Description The IDT70V38 is a high-speed 64K x 18 Dual-Port Static RAM. The IDT70V38 is designed to be used as a stand-alone 1152K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port ...

Page 3

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Pin Names Left Port Right Port Chip Enables , R/W R/W Read/Write Enable L R Output Enable ...

Page 4

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Truth Table I – Chip Enable < 0. >V -0.2V CC (3) X NOTES: 1. Chip Enable references are shown above ...

Page 5

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL ...

Page 6

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Waveform of Read Cycles ADDR ( UB, LB R/W DATA OUT ...

Page 7

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE ...

Page 8

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE (9,10 SEM ( ( R/W DATA OUT DATA IN Timing Waveform of ...

Page 9

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM I R/W OE NOTES ...

Page 10

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match BAA t BUSY Disable Time from Address ...

Page 11

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES: 1. ...

Page 12

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by ...

Page 13

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" CE "A" R/W "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ...

Page 14

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Truth Table V — Address BUSY Arbitration Inputs Outputs 15L BUSY 15R MATCH ...

Page 15

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses ...

Page 16

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM it proceeds to assume control over the shared resource was not successful in setting the latch, it determines that the right side processor has set the latch first, has ...

Page 17

IDT70V38L High-Speed 3.3V 64K x 18 Dual-Port Static RAM Ordering Information IDT XXXXX A 999 Device Power Speed Package Type NOTE: 1. Contact your sales office for Industrial Temperature range in other speeds, packages and powers. Datasheet Document History: 08/01/99: ...

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