IDT72275 IDT [Integrated Device Technology], IDT72275 Datasheet

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... Slim Thin Quad Flat Pack (STQFP) • High-performance submicron CMOS technology DESCRIPTION: The IDT72275/72285 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improve- ments over previous SuperSync FIFOs, including the following: • ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 x 18 DESCRIPTION (Continued) delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.) SuperSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data. ...

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... Initiating any operation (by activating control LD inputs) will immediately take the device out of the power down on each rising state. The IDT72275/72285 are fabricated using IDT’s high speed submicron CMOS technology. PARTIAL RESET ( ) MASTER RESET ( ) LOAD ( ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable OE Output Enable ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 ELECTRICAL CHARACTERISTICS (Commercial 10 Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time CLKL t Data Setup Time DS t Data Hold Time ...

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... When the FIFO is full, the Input Ready ( inhibiting further write operations reads are performed after a reset 32,769 writes for the IDT72275 and 65,537 writes for the IDT72285, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register. ...

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... PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72275/72285 has internal registers for these offsets. Default settings are stated in the footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO in one of two ways; serial or parallel loading method. The selection of the loading method is done using the pin ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 x 18 72275 (32,768 x 18–BIT EMPTY OFFSET REGISTER DEFAULT VALUE 007FH if is LOW at Master Reset, 03FFH if is HIGH at Master Reset FULL OFFSET REGISTER DEFAULT VALUE 007FH if is LOW at Master Reset, 03FFH if is HIGH at Master Reset ...

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... WCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. A total of 30 bits for the IDT72275 and 32 bits for the IDT72285. See Figure 13, Serial Loading of Programmable Flag Regis- ters , for the timing diagram for this mode. ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 x 18 change in level will only be noticeable if setup. During this period, the internal read pointer is initialized to the first location of the RAM array. EF When goes HIGH, Retransmit setup is complete and read operations may begin starting with the first location in memory ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 x 18 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS: MRS MRS MRS MRS MRS MASTER RESET ( ) A Master Reset is accomplished whenever the is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array ...

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... FIFO is not full reads are performed after a reset (either MRS or SKEW (D = 32,768 for the IDT72275 and 65,536 for the IDT72285). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode) , for the relevant timing information the third valid LOW ...

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... HIGH, inhibiting further write operations reads are MRS performed after a reset (either after D writes to the FIFO (D = 32,769 for the IDT72275 and 65,537 for the IDT72285) See Figure 9, Write Timing (FWFT Mode) , for the relevant timing information. IR ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 FWFT FWFT/ RSS t RSS t RSS t RSS t RSS t If FWFT = HIGH, RSF If FWFT = LOW, t RSF If FWFT = LOW, If FWFT = HIGH, t RSF t RSF t RSF Figure 5. Master Reset Timing COMMERCIAL TEMPERATURE RANGE t RSR t RSR ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 RSS t RSS t RSS t RSS t RSF t RSF t RSF t RSF t RSF Figure 6. Partial Reset Timing COMMERCIAL TEMPERATURE RANGE t RSR t RSR If FWFT = HIGH, = HIGH If FWFT = LOW, = LOW If FWFT = LOW, = HIGH If FWFT = HIGH, = LOW ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 WRITE WCLK 1 (1) t SKEW1 RCLK t t ENS ENH DATA IN OUTPUT REGISTER NOTES the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that SKEW1 If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than t extra WCLK cycle ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 x 18 COMMERCIAL TEMPERATURE RANGE 18 ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 x 18 COMMERCIAL TEMPERATURE RANGE 19 ...

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... FIFO after Master Reset more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, Retransmit setup procedure 32,768 for IDT72275 and 65,536 for IDT72285 goes HIGH RCLK cycle + t ...

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... OR 5. goes LOW RCLK cycles + t WCLK t ENS t LDS BIT 0 NOTE for the IDT72275 and for the IDT72285. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF PAF ...

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... D = maximum FIFO depth. In IDT Standard mode 32,768 for the IDT72275 and 65,536 for the IDT72285. In FWFT mode 32,769 for the IDT72275 and 65,537 for the IDT72285 the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that ...

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... RCLK NOTES: 1. For IDT Standard mode maximum FIFO depth 32,768 for the IDT72275 and 65,536 for the IDT72285. 2. For FWFT mode maximum FIFO depth 32,769 for the IDT72275 and 65,537 for the IDT72285. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...

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... Figure 19. Block Diagram of 32,768 x 36 and 65,536 x 36 Width Expansion DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72275 can easily be adapted to applications requir- ing depths greater than 32,768 and 65,536 for the IDT72285 with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...

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... IDT72275/72285 SUPERSYNC FIFO™ 32,768 x 18, 65,536 x 18 FWFT/SI • FWFT/SI WRITE CLOCK WCLK WRITE ENABLE IDT INPUT READY 72275 72285 n DATA IN Dn Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion between WCLK and transfer clock, or RCLK and transfer ...