C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 121

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

13.6.1. Internal XRAM Only
When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the
device. Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries
(depending on the RAM available on the device). As an example, the addresses 0x1000 and 0x2000 both
evaluate to address 0x0000 in on-chip XRAM space.
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13.6.2. Split Mode without Bank Select
When EMI0CF.[3:2] are set to ‘01’, the XRAM memory map is split into two areas, on-chip space and
off-chip space.
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8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is
on-chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus
A[7:0] are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is
on-chip or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are
driven during the off-chip transaction.
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Rev. 1.3
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