EP7311-CV Cirrus Logic Inc, EP7311-CV Datasheet - Page 8

• Manufacturer Part Number: EP7311-CV
• Description: Low-Power Processor 208-Pin LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP7r

Specifications of EP7311-CV

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 74MHz
• Connectivity: Codec, EBI/EMI, IrDA, Keypad, Multimedia Codec, SPI/Microwire1, UART/USART
• Peripherals: LCD, LED, MaverickKey, PWM
• Number Of I /o: 27
• Program Memory Type: ROMless
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.7 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-LQFP
• Processor Series: EP73xx
• Core: ARM720T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1224

EP7311
High-Performance, Low-Power System on Chip
CODEC Interface
The EP7311 includes an interface to telephony-type CODECs
for easy integration into voice-over-IP and other voice
communications
multiplexed to the same pins as the MCP and SSI2.
SSI2 Interface
An
available for both master and slave mode communications. The
SSI2 unit shares the same pins as the MCP and CODEC
interfaces through a multiplexer.
•
•
•
•
8
PCMCLK
PCMOUT
PCMIN
PCMSYNC
SSICLK
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
Note:
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/full interrupts for FIFOs
Separate RX and TX frame sync signals for asymmetric
traffic
Note:
Pin Mnemonic
Pin Mnemonic
additional
See
See
multiplexes.
multiplexes.
Table F. CODEC Interface Pin Assignments
Table G. SSI2 Interface Pin Assignments
Table R on page 11
Table R on page 11
SPI/Microwire1-compatible
systems.
I/O
O
O
O
I
I/O
I/O
I/O
I/O
The
O
I
for information on pin
for information on pin
Serial bit clock
Serial data out
Serial data in
Frame sync
CODEC
Serial bit clock
Serial data out
Serial data in
Transmit frame sync
Receive frame sync
Pin Description
Pin Description
©
Copyright Cirrus Logic, Inc. 2005
interface
interface
(All Rights Reserved)
is
is
Synchronous Serial Interface
•
•
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The display
frame buffer start address is programmable, allowing the LCD
frame buffer to be in SDRAM, internal SRAM or external
SRAM.
•
•
•
•
•
ADCLK
ADCIN
ADCOUT
nADCCS
SMPCLK
CL1
CL2
DD[3:0]
FRM
M
Pin Mnemonic
ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
Selectable serial clock polarity
Interfaces directly to a single-scan panel monochrome STN
LCD
Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
Panel width size is programmable from 32 to 1024 pixels in
16-pixel increments
Video frame buffer size programmable up to
128 KB
Bits per pixel of 1, 2, or 4 bits
Pin Mnemonic
Table H. Serial Interface Pin Assignments
Table I. LCD Interface Pin Assignments
I/O
O
O
O
O
O
I/O
O
O
O
O
I
LCD line clock
LCD pixel clock out
LCD serial display data bus
LCD frame synchronization pulse
LCD AC bias drive
SSI1 ADC serial clock
SSI1 ADC serial input
SSI1 ADC serial output
SSI1 ADC chip select
SSI1 ADC sample clock
Pin Description
Pin Description
DS506F1