CY37064P100-125AXI Cypress Semiconductor Corp, CY37064P100-125AXI Datasheet - Page 13

• Manufacturer Part Number: CY37064P100-125AXI
• Description: CPLD Ultra37000™ Family 2K Gates 64 Macro Cells 125MHz CMOS Technology 5V 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultra37000™r

Specifications of CY37064P100-125AXI

• Package: 100TQFP
• Family Name: Ultra37000™
• Device System Gates: 2000
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 69
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 125 MHz
• Number Of Product Terms Per Macro: 16
• Operating Temperature: -40 to 85 °C
• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Macrocells: 64
• Number Of I /o: 69
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Voltage: 5V
• Memory Type: CMOS
• # Macrocells: 64
• Number Of Usable Gates: 2000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• # I/os (max): 69
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-1936; CY37064P100-125AXI

Document #: 38-03007 Rev. *E
Logic Block Diagrams
CY37512/CY37512V
TDI
TCK
TMS
JTAG Tap
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
108
120
96
12
24
36
48
60
72
84
−I/O
−I/O
0
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
131
107
119
11
23
35
47
59
71
83
95
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
(continued)
TDO
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
4
132
AO
AG
AN
AA
AB
AC
AD
AE
AF
AK
AL
AM
AP
AH
AJ
AI
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
1
Input Clock/ Input
PIM
4
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
16
36
16
36
16
36
16
36
16
36
36
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
BM
BB
BP
BO
BN
BK
BH
BG
BF
BE
BC
BA
BL
BJ
BD
BI
132
4
Ultra37000 CPLD Family
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
144
252
240
228
216
192
180
156
132
204
168
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
155
263
251
239
227
203
191
167
143
215
179
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