XC2C512-10FT256C Xilinx Inc, XC2C512-10FT256C Datasheet - Page 24

• Manufacturer Part Number: XC2C512-10FT256C
• Description: CPLD CoolRunner™-II Family 12K Gates 512 Macro Cells 128MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2C512-10FT256C

• Package: 256FTBGA
• Family Name: CoolRunner™-II
• Device System Gates: 12000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 212
• Number Of Logic Blocks/elements: 32
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 128 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: 0 to 70 °C

XC2C512 CoolRunner-II CPLD
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
Additional information is available for the following CoolRunner-II topics:
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Revision History
The following table shows the revision history for this document.
24
11/25/03
10/01/04
01/30/05
03/07/05
03/20/06
02/15/07
03/08/07
7/19/02
3/15/03
1/26/04
8/03/04
XAPP784: Bulletproof CPLD Design Practices
XAPP375: Timing Model
XAPP376: Logic Engine
XAPP378: Advanced Features
XAPP382: I/O Characteristics
XAPP389: Powering CoolRunner-II
XAPP399: Assigning VREF Pins
Date
Version
1.0
2.0
2.1
2.2
2.3
2.4
2.5
2.6
3.0
3.1
3.2
Initial Xilinx release.
Added characterization data.
Fixed two typos.
Updated Tsol; added links to Data Sheets and Application Notes.
Pb-free documentation
Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
Change to I
Removed -6 speed grade. Modified Table 1, IOSTANDARDs.
Change to Product Specification. Add warranty Disclaimer. Add note to Pin Descriptions
that
Corrections to timing parameters t
t
t
changes to silicon or characterization. Added XC2C512-7FT256I and XC2C512-7FTG236I
packages. Change to V
Fixed typo in note for V
OUT
PHD
GCK, GSR, and GTS pins can also be used for general purpose I/O.
(SSTL3), and t
, and t
PH
CCSB
for the -7 speed grade. Values now match the software. There were no
MAX for Commercial and Industrial.
Tin
(SSTL3) for -6 speed grade. Corrections to t
www.xilinx.com
IL
IH
for LVCMOS18; removed note for V
specification for 2.5V and 1.8V LVCMOS.
To access these and all application notes with their associ-
ated reference designs, click the following link and scroll
down the page until you find the document you want:
CoolRunner-II Data Sheets and Application Notes
Device Packages
DIN
, t
SUD
Revision
, t
PSUD
, t
PHD
, t
PH
, t
IL
SLEW18
for LVCMOS33.
DS096 (v3.2) March 8, 2007
DIN
, t
, t
Product Specification
IN
SUD
(HSTL),
, t
CO
, t
PSUD
,
R