XC2S100E-6PQG208C Xilinx Inc, XC2S100E-6PQG208C Datasheet - Page 46

FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP

XC2S100E-6PQG208C

Manufacturer Part Number
XC2S100E-6PQG208C
Description
FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-IIEr
Datasheet

Specifications of XC2S100E-6PQG208C

Package
208PQFP
Family Name
Spartan®-IIE
Device Logic Cells
2700
Device Logic Units
600
Device System Gates
100000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
146
Ram Bits
40960
Number Of Logic Elements/cells
2700
Number Of Labs/clbs
600
Total Ram Bits
40960
Number Of I /o
146
Number Of Gates
100000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Spartan-IIE FPGA Family: DC and Switching Characteristics
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
46
Combinatorial Delays
Multiplier Operation
Setup/Hold Times with Respect to Clock CLK
T
T
CCKX
CCKY
T
T
T
T
T
T
T
Symbol
T
T
T
T
T
T
T
GANDCY
FANDCY
GANDYB
T
T
FANDXB
FANDYB
T
T
OPGYB
OPCYG
OPCYF
T
CINXB
CINYB
OPXB
OPYB
OPGY
BXCY
CINX
CINY
OPX
OPY
BYP
/ T
/ T
CKCX
CKCY
F operand inputs to X via XOR
F operand input to XB output
F operand input to Y via XOR
F operand input to YB output
F operand input to COUT output
G operand inputs to Y via XOR
G operand input to YB output
G operand input to COUT output
BX initialization input to COUT
CIN input to X output via XOR
CIN input to XB
CIN input to Y via XOR
CIN input to YB
CIN input to COUT output
F1/2 operand inputs to XB output via AND
F1/2 operand inputs to YB output via AND
F1/2 operand inputs to COUT output via AND
G1/2 operand inputs to YB output via AND
G1/2 operand inputs to COUT output via AND
CIN input to FFX
CIN input to FFY
Description
www.xilinx.com
1.2 / 0
1.2 / 0
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-7
Max
0.51
0.07
0.14
0.35
0.8
0.8
1.4
1.1
0.9
0.8
1.2
0.9
0.6
0.7
0.4
0.7
0.5
0.6
0.3
Speed Grade
-
-
1.3 / 0
1.3 / 0
Min
DS077-3 (v2.3) June 18, 2008
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-6
Product Specification
Max
0.15
0.8
0.9
1.5
1.3
1.0
0.9
1.3
1.0
0.6
0.7
0.1
0.7
0.5
0.4
0.8
0.6
0.7
0.4
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R

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