XC2S100E-6TQ144C Xilinx Inc, XC2S100E-6TQ144C Datasheet - Page 61

• Manufacturer Part Number: XC2S100E-6TQ144C
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-IIEr

Specifications of XC2S100E-6TQ144C

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960
• Number Of Logic Elements/cells: 2700
• Number Of Labs/clbs: 600
• Total Ram Bits: 40960
• Number Of I /o: 102
• Number Of Gates: 100000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-LQFP
• Case: TQFP144
• Dc: 05+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1206

In the PQ208 package, all VCCO pins must be connected to
the same voltage.
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
DS077-4 (2.3) June 18, 2008
Product Specification
GND
TMS
I/O
I/O
I/O
I/O, VREF
Bank 7,
L49P
I/O, L49N
I/O
I/O
I/O, L48P
I/O, L48N
GND
VCCO
VCCINT
I/O,
L47P_YY
I/O,
L47N_YY
I/O,
L46P_YY
I/O,
L46N_YY
GND
I/O, VREF
Bank 7,
L45P
I/O, L45N
Function
Pad Name
R
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
-
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
Pin
P1
P2
P3
P4
P5
P6
P7
P8
P9
150E, 200E,
150E, 200E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
Async.
Output
Option
LVDS
300E
300E
300E
300E
300E
300E
All
All
All
All
-
-
-
-
-
-
-
-
-
-
-
150E, 200E,
XC2S200E,
XC2S100E,
Option
300E
300E
V
All
All
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
I/O
I/O,
L44P_YY
I/O (IRDY),
L44N_YY
GND
VCCO
I/O (TRDY)
VCCINT
I/O
I/O, L43P
I/O, VREF
Bank 6,
L43N
GND
I/O,
L42P_YY
I/O,
L42N_YY
I/O,
L41P_YY
I/O,
L41N_YY
VCCINT
VCCO
GND
I/O, L40P
I/O, L40N
I/O
I/O
I/O
Function
Pad Name
Bank
Spartan-IIE FPGA Family: Pinout Tables
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
-
-
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
Pin
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
Async.
Output
Option
LVDS
300E
300E
300E
300E
All
All
All
All
All
All
-
-
-
-
-
-
-
-
-
-
-
-
-
150E, 200E,
XC2S100E,
Option
V
300E
All
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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