XC2S400E-6FTG256C Xilinx Inc, XC2S400E-6FTG256C Datasheet - Page 3

• Manufacturer Part Number: XC2S400E-6FTG256C
• Description: FPGA Spartan®-IIE Family 400K Gates 10800 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S400E-6FTG256C

• Package: 256FTBGA
• Family Name: Spartan®-IIE
• Device Logic Cells: 10800
• Device Logic Units: 2400
• Device System Gates: 400000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 182
• Ram Bits: 163840
• Case: BGA
• Dc: 04+

DS077-1 (v2.3) June 18, 2008
Introduction
The Spartan
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
seven-member family offers densities ranging from 50,000
to 600,000 system gates, as shown in
formance is supported beyond 200 MHz.
Features include block RAM (to 288K bits), distributed RAM
(to 221,184 bits), 19 selectable I/O standards, and four
DLLs (Delay-Locked Loops). Fast, predictable interconnect
means that successive design iterations continue to meet
timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
•
•
Table 1: Spartan-IIE FPGA Family Members
Notes:
1.
© 2003-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS077-1 (v2.3) June 18, 2008
Product Specification
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC2S50E
Device
Second generation ASIC replacement technology
-
-
-
-
-
System level features
-
User I/O counts include the four global clock/user input pins. See details in
Densities as high as 15,552 logic cells with up to
600,000 system gates
Streamlined features based on Virtex
architecture
Unlimited in-system reprogrammability
Very low cost
Cost-effective 0.15 micron technology
SelectRAM™ hierarchical memory:
·
·
development
16 bits/LUT distributed RAM
Configurable 4K-bit true dual-port block RAM
®
-IIE Field-Programmable Gate Array family
10,800
15,552
Logic
Cells
1,728
2,700
3,888
5,292
6,912
cycles,
System Gate Range
145,000 - 400,000
210,000 - 600,000
(Logic and RAM)
37,000 - 100,000
52,000 - 150,000
71,000 - 200,000
93,000 - 300,000
23,000 - 50,000
R
Typical
and
Table
inherent
1. System per-
®
-E FPGA
16 x 24
20 x 30
24 x 36
28 x 42
32 x 48
40 x 60
48 x 72
(R x C)
Array
risk
CLB
www.xilinx.com
of
0
CLBs
1,176
1,536
2,400
3,456
Total
384
600
864
Spartan-IIE FPGA Family:
Introduction and Ordering
Information
Product Specification
•
•
•
-
-
-
-
-
-
-
-
-
Versatile I/O and packaging
-
-
-
-
-
-
Core logic powered at 1.8V and I/Os powered at 1.5V,
2.5V, or 3.3V
Fully supported by powerful Xilinx
system
-
-
-
User I/O
Maximum
Available
·
Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
Low-power segmented routing architecture
Dedicated carry logic for high-speed arithmetic
Efficient multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
·
·
Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
Pb-free package options
Low-cost packages available in all densities
Family footprint compatibility in common packages
19 high-performance interface standards
·
·
Up to 205 differential I/O pairs that can be input,
output, or bidirectional
Hot swap I/O (CompactPCI friendly)
Fully automatic mapping, placement, and routing
Integrated with design entry and verification tools
Extensive IP library including DSP functions and
soft processors
Table 2, page 5
182
202
265
289
329
410
514
Fast interfaces to external RAM
Eliminate clock distribution delay
Multiply, divide, or phase shift
LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
LVDS and LVPECL differential I/O
(1)
Differential
Maximum
I/O Pairs
114
120
120
172
205
83
86
Distributed
RAM Bits
153,600
221,184
24,576
38,400
55,296
75,264
98,304
®
ISE
®
development
Block RAM
160K
288K
Bits
32K
40K
48K
56K
64K
3