XC2V1000-5FG456I Xilinx Inc, XC2V1000-5FG456I Datasheet - Page 25

• Manufacturer Part Number: XC2V1000-5FG456I
• Description: FPGA Virtex-II™ Family 1M Gates 11520 Cells 750MHz 0.15um/0.12um (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V1000-5FG456I

• Package: 456FBGA
• Family Name: Virtex-II™
• Device Logic Units: 11520
• Device System Gates: 1000000
• Number Of Registers: 10240
• Maximum Internal Frequency: 750 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 324
• Ram Bits: 737280
• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 324
• Number Of Gates: 1000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Multiplexers
Virtex-II function generators and associated multiplexers
can implement the following:
•
•
•
•
Fast Lookahead Carry Logic
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II CLB has two separate carry
chains, as shown in the
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II device is running upward. The dedi-
cated carry path and carry multiplexer (MUXCY) can also
DS031-2 (v3.5) November 5, 2007
Product Specification
4:1 multiplexer in one slice
8:1 multiplexer in two slices
16:1 multiplexer in one CLB element (4 slices)
32:1 multiplexer in two CLB elements (8 slices)
R
G
G
F
F
Figure
24.
Figure 23: MUXF5 and MUXFX multiplexers
Slice S3
Slice S2
Slice S1
Slice S0
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G
G
F
F
Each Virtex-II slice has one MUXF5 multiplexer and one
MUXFX multiplexer. The MUXFX multiplexer implements
the MUXF6, MUXF7, or MUXF8, as shown in
Each CLB element has two MUXF6 multiplexers, one
MUXF7 multiplexer and one MUXF8 multiplexer. Examples
of multiplexers are shown in the Virtex-II Platform FPGA
User Guide. Any LUT can implement a 2:1 multiplexer.
be used to cascade function generators for implementing
wide logic functions.
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND (MULT_AND) gate (shown in
improves the efficiency of multiplier implementation.
CLB
Virtex-II Platform FPGAs: Functional Description
MUXF8 combines
the two MUXF7 outputs
(Two CLBs)
MUXF6 combines the two MUXF5
outputs from slices S2 and S3
MUXF7 combines the two MUXF6
outputs from slices S0 and S2
MUXF6 combines the two MUXF5
outputs from slices S0 and S1
DS031_08_100201
Module 2 of 4
Figure
Figure
23.
16)
17