XC2V1000-5FG456I Xilinx Inc, XC2V1000-5FG456I Datasheet - Page 4

• Manufacturer Part Number: XC2V1000-5FG456I
• Description: FPGA Virtex-II™ Family 1M Gates 11520 Cells 750MHz 0.15um/0.12um (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V1000-5FG456I

• Package: 456FBGA
• Family Name: Virtex-II™
• Device Logic Units: 11520
• Device System Gates: 1000000
• Number Of Registers: 10240
• Maximum Internal Frequency: 750 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 324
• Ram Bits: 737280
• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 324
• Number Of Gates: 1000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Architecture
Virtex-II Array Overview
Virtex-II devices are user-programmable gate arrays with
various configurable elements. The Virtex-II architecture is
optimized for high-density and high-performance logic
designs. As shown in
comprised of input/output blocks (IOBs) and internal
configurable logic blocks (CLBs).
The internal configurable logic includes four major elements
organized in a regular array.
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•
•
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A new generation of programmable routing resources called
Active Interconnect Technology interconnects all of these
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.
All
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
DS031-1 (v3.5) November 5, 2007
Product Specification
Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
Block SelectRAM memory modules provide large
18 Kbit storage elements of dual-port RAM.
Multiplier blocks are 18-bit x 18-bit dedicated
multipliers.
DCM (Digital Clock Manager) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, coarse- and fine-grained clock phase
shifting.
programmable
R
Figure
elements,
1, the programmable device is
Programmable I/Os
Configurable Logic
Global Clock Mux
including
Figure 1: Virtex-II Architecture Overview
the
routing
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CLB
Programmable I/O blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported by
the programmable IOBs.
configuration and can be reloaded to change the functions
of the programmable elements.
Virtex-II Features
This section briefly describes Virtex-II features.
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
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These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
•
•
•
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Block SelectRAM
DCM
Virtex-II Platform FPGAs: Introduction and Overview
Input block with an optional single-data-rate or
double-data-rate (DDR) register
Output block with an optional single-data-rate or DDR
register, and an optional 3-state buffer, to be driven
directly or through a single or DDR register
Bidirectional block (any combination of input and output
configurations)
LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
PCI-X compatible (133 MHz and 66 MHz) at 3.3V
PCI compliant (66 MHz and 33 MHz) at 3.3V
CardBus compliant (33 MHz) at 3.3V
GTL and GTLP
DCM
Multiplier
DS031_28_100900
IOB
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