XC3S1200E-4FT256C Xilinx Inc, XC3S1200E-4FT256C Datasheet - Page 85

• Manufacturer Part Number: XC3S1200E-4FT256C
• Description: FPGA Spartan®-3E Family 1.2M Gates 19512 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S1200E-4FT256C

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 19512
• Device Logic Units: 2168
• Device System Gates: 1200000
• Number Of Registers: 17344
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 516096

Byte-Wide Peripheral Interface (BPI) Parallel
Flash Mode
For additional information, refer to the “Master BPI Mode”
chapter in UG332.
In
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA config-
ures itself from an industry-standard parallel NOR Flash
PROM, as illustrated in
to a 24-bit address lines to access an attached parallel
Flash. Only 20 address lines are generated for Spartan-3E
FPGAs in the TQ144 package. Similarly, the XC3S100E
FPGA in the CP132 package only has 20 address lines
while the XC3S250E and XC3S500E FPGAs in the same
package have 24 address lines. When using the VQ100
package, the BPI mode is not available when using parallel
NOR Flash, but is supported using parallel Platform Flash
(XCFxxP).
The BPI configuration interface is primarily designed for
standard parallel NOR Flash PROMs and supports both
byte-wide (x8) and byte-wide/halfword (x8/x16) PROMs.
The interface functions with halfword-only (x16) PROMs,
DS312-2 (v3.8) August 26, 2009
Product Specification
Byte-wide
R
Peripheral
Figure
58. The FPGA generates up
Interface
(BPI)
mode
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but the upper byte in a portion of the PROM remains
unused. For configuration, the BPI interface does not
require any specific Flash PROM features, such as boot
block or a specific sector size.
The BPI interface also functions with Xilinx parallel Platform
Flash PROMs (XCFxxP), although the FPGA’s address
lines are left unconnected.
The BPI interface also works equally wells with other asyn-
chronous memories that use a similar SRAM-style interface
such as SRAM, NVRAM, EEPROM, EPROM, or masked
ROM.
NAND Flash memory is commonly used in memory cards
for digital cameras. Spartan-3E FPGAs do not configure
directly from NAND Flash memories.
The FPGA’s internal oscillator controls the interface timing
and the FPGA supplies the clock on the CCLK output pin.
However, the CCLK signal is not used in single FPGA appli-
cations. Similarly, the FPGA drives three pins Low during
configuration (LDC[2:0]) and one pin High during configura-
tion (HDC) to the PROM’s control inputs.
Functional Description
85