XC3S1200E-4FGG320I Xilinx Inc, XC3S1200E-4FGG320I Datasheet
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R DS312 (v3.8) August 26, 2009 Module 1: Spartan-3E FPGA Family: Introduction and Ordering Information DS312-1 (v3.8) August 26, 2009 • Introduction • Features • Architectural Overview • Package Marking • Ordering Information Module 2: Functional Description DS312-2 (v3.8) August ...
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Spartan-3E FPGA Family: Data Sheet 2 www.xilinx.com R DS312 (v3.8) August 26, 2009 Product Specification ...
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... XC3S250E 250K 5,508 34 XC3S500E 500K 10,476 46 XC3S1200E 1200K 19,512 60 XC3S1600E 1600K 33,192 76 Notes convention, one Kb is equivalent to 1,024 bits. © 2005–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun- tries ...
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... Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. Notes: 1. The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom. 4 • ...
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... XC3S250E (7) (2) (7) ( XC3S500E (7) (2) (7) XC3S1200E - - - XC3S1600E - - - Notes: 1. All Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4: 2. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. ...
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Package Marking Figure 2 provides a top marking example for Spartan-3E FPGAs in the quad-flat packages. marking for Spartan-3E FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the BGA packages are nearly identical ...
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... Device Type Speed Grade Package Type Device Speed Grade XC3S100E –4 Standard Performance XC3S250E –5 High Performance XC3S500E XC3S1200E XC3S1600E Notes: 1. The –5 speed grade is exclusively available in the Commercial temperature range. 2. The XC3S500E VQG100 is available only in the -4 Speed Grade. 3. See DS635 for the XA Automotive Spartan-3E FPGAs ...
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Revision History The following table shows the revision history for this document. Date Version 03/01/05 1.0 Initial Xilinx release. 03/21/05 1.1 Added XC3S250E in CP132 package to for CP132 package. Added package markings for QFP packages CP132/CPG132 packages 11/23/05 2.0 ...
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R DS312-2 (v3.8) August 26, 2009 Design Documentation Available The functionality of the Spartan®-3E FPGA family is now described and updated in the following documents. The topics covered in each guide are listed below. • UG331: Spartan-3 Generation FPGA User ...
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Functional Description Introduction As described in Architectural Overview, the Spartan™-3E FPGA architecture consists of five fundamental functional elements: • Input/Output Blocks (IOBs) • Configurable Logic Block (CLB) and Slice Resources • Block RAM • Dedicated Multipliers • Digital Clock Managers ...
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TCE T2 O1 OTCLK1 OCE O2 OTCLK2 I IQ1 D IDDRIN1 IDDRIN2 CE ICLK1 CK ICE IQ2 D CE ICLK2 CK SR REV Notes: 1. All IOB control and output path signals have an ...
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Functional Description Input Delay Functions Each IOB has a programmable delay block that optionally delays the input signal. In Figure 6, the signal path has a coarse delay element that can be bypassed. The input sig- nal then feeds a ...
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R Storage Element Functions There are three pairs of storage elements in each IOB, one pair for each of the three paths possible to configure each of these storage elements as an edge-triggered D-type flip-flop (FD ...
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Functional Description Table 5: Storage Element Options (Continued) Option Switch SRHIGH/SRLOW Determines whether SR acts as a Set, which forces the storage element to a logic "1" (SRHIGH Reset, which forces a logic "0" (SRLOW) INIT1/INIT0 When Global ...
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R Register Cascade Feature In the Spartan-3E family, one of the IOBs in a differential pair can cascade its input storage elements with those in the other IOB as part of a differential pair. This is intended to make DDR ...
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Functional Description D D1 From Fabric D2 D OCLK1 OCLK2 OCLK1 OCLK2 d D1 d+2 d+4 D2 d+1 d+3 d+5 PAD d d+1 d+2 d+3 d+4 Figure 10: Output DDR Table 6: Single-Ended IOSTANDARD Bank Compatibility Single-Ended IOSTANDARD 1.2V LVTTL ...
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R Table 6: Single-Ended IOSTANDARD Bank Compatibility (Continued) Single-Ended IOSTANDARD 1.2V SSTL18_I - SSTL2_I - Notes: 1. N/R - Not required for input operation. Table 7: Differential IOSTANDARD Bank Compatibility Differential IOSTANDARD 1.8V LVDS_25 Input RSDS_25 Input MINI_LVDS_25 Input LVPECL_25 ...
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Functional Description V provides current to the outputs and additionally pow- CCO ers the On-Chip Differential Termination. V 2.5V when using the On-Chip Differential Termination. The V lines are not required for differential operation. REF To further understand how to ...
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R Table 8: Programmable Output Drive Current Output Drive Current (mA IOSTANDARD LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 - - High output current drive strength and FAST output slew rates generally result in fastest I/O performance. However, these same ...
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Functional Description exception for differential inputs (IP_Lxxx_x). For the differ- ential Dedicated Inputs, the on-chip differential termination is not available. To replace the on-chip differential termina- tion, choose a differential pair that supports outputs (IO_Lxxx_x) or use an external 100Ω ...
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... Device Rows Columns XC3S100E 22 16 XC3S250E 34 26 XC3S500E 46 34 XC3S1200E 60 46 XC3S1600E 76 58 Notes: 1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are embedded in the array (see Figure 1 Slices Each CLB comprises four interconnected slices, as shown ...
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Functional Description . Notes: 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. The index i can depending on the slice. The upper ...
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R Switch Matrix SHIFTOUT Slice Location Designations The Xilinx development software designates the location of a slice according to its X and Y coordinates, starting in the bottom left corner, as shown in Figure lowed by a number identifies columns ...
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Functional Description The SLICEM pair supports two additional functions: • Two 16x1 distributed RAM blocks, RAM16 • Two 16-bit shift registers, SRL16 Each of these elements is described in more detail in the fol- lowing sections. Logic Cells The combination ...
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R Table 10: Slice Inputs and Outputs (Continued) Name Location CLK SLICEL/M Common SHIFTIN SLICEM Top SHIFTOUT SLICEM Bottom CIN SLICEL/M Bottom COUT SLICEL/M Top X SLICEL/M Bottom Y SLICEL/M Top XB SLICEL/M Bottom YB SLICEL/M Top XQ SLICEL/M Bottom ...
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Functional Description ing LUTs or by using the wide function multiplexers that are described later. The output of the LUT can connect to the wide multiplexer logic, the carry and arithmetic logic, or directly to a CLB out- put or ...
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R Figure 20: MUXes and Dedicated Feedback in Spartan-3E CLB Table 11: MUX Capabilities MUX Usage F5MUX F5MUX FiMUX F6MUX F7MUX F8MUX DS312-2 (v3.8) August 26, 2009 Product Specification FXINB F8 FXINA F5 FXINB F6 FXINA F5 FXINB FX F7 ...
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Functional Description The wide multiplexers can be used by the automatic tools or instantiated in a design using a component such as the F5MUX. The symbol, signals, and function are described below. The description is similar for the F6MUX, F7MUX, ...
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R G[4: F[4: Table 14: Carry Logic Functions Function CYINIT Initializes carry chain for a slice. Fixed selection of: • CIN carry input from the slice below • BX input CY0F Carry generation for bottom ...
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Functional Description Table 14: Carry Logic Functions (Continued) Function CYMUXG Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of: • CYMUXF carry propagation (CYSELG = 1) • CY0G carry generation (CYSELG = 0) CYSELF ...
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R The MULT_AND is useful for small multipliers. Larger multi- pliers can be built using the dedicated 18x18 multiplier blocks (see Dedicated Multipliers). Storage Elements The storage element, which is programmable as either a D-type flip-flop or a level-sensitive transparent ...
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Functional Description Initialization The CLB storage elements are initialized at power-up, dur- ing configuration, by the global GSR signal, and by the indi- vidual SR or REV inputs to the CLB. The storage elements can also be re-initialized using the ...
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R D A[3:0] WE WCLK DPRA[3:0] RAM16X1D WE D WCLK DPRA0 DPRA1 DPRA2 DPRA3 DS312-2_42_021305 Figure 27: Dual-Port RAM Component Table 18: Dual-Port RAM Function Inputs WE (mode) WCLK D 0 (read (read) ...
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Functional Description The INIT attribute can be used to preload the memory with data during FPGA configuration. The default initial contents for RAM is all zeros. If the WE is held Low, the element can be considered a ROM. The ...
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... XC3S100E 4 73,728 XC3S250E 12 221,184 XC3S500E 20 368,640 XC3S1200E 28 516,096 XC3S1600E 36 663,552 Immediately adjacent to each block RAM is an embedded 18x18 hardware multiplier. The upper 16 bits of the block RAM's Port A Data input bus are shared with the upper 16 bits of the A multiplicand input bus of the multiplier. Similarly, the upper 16 bits of Port B's data input bus are shared with the B multiplicand input bus of the multiplier ...
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Functional Description Table 22: Port Aspect Ratios DIP/DOP Total Data DI/DO Data Parity Bus Path Width Bus Width Width 1 (w bits) (w-p bits) (p bits Notes: 1. ...
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R Parity 512x36 Figure 31: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B DS312-2 (v3.8) August 26, 2009 Product Specification Data ...
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Functional Description Block RAM Port Signal Definitions Representations of the RAMB16_S[w ]_S[w ] and the A B RAMB16_S[w] with their associated signals are shown in Figure 32a and Figure 32b, respectively. These signals are defined in Table 23. The control ...
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R Table 23: Block RAM Port Signals Port A Port B Signal Signal Signal Description Name Name Address Bus ADDRA ADDRB Data Input Bus DIA DIB Parity Data DIPA DIPB Input(s) Data Output Bus DOA DOB Parity Data DOPA DOPB ...
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Functional Description Block RAM Attribute Definitions A block RAM has a number of attributes that control its behavior as shown in Table 24. Table 24: Block RAM Attributes Function Initial Content for Data Memory, Loaded during Configuration Initial Content for ...
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R Table 25: Block RAM Function Table (Continued) Input Signals GSR EN SSR WE CLK ↑ There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access ...
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Functional Description Data_in CLK WE DI ADDR DO 0000 EN DISABLED Figure 33: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected Setting the WRITE_MODE attribute to a value of WRITE_FIRST, data is written to the addressed memory location on ...
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R Data_in CLK WE DI ADDR DO 0000 EN DISABLED Figure 35: Waveforms of Block RAM Data Operations with NO_CHANGE Selected Setting the WRITE_MODE attribute to a value of NO_CHANGE, puts the DO outputs in a latched state when asserting ...
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Functional Description Dedicated Multipliers For additional information, refer to the “Using Embedded Multipliers” chapter in UG331. The Spartan-3E devices provide dedicated multiplier blocks per device. The multipliers are located together with the block RAM in one or ...
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R MULT18X18SIO A[17:0] B[17:0] CEA CEB CEP CLK RSTA RSTB RSTP BCIN[17:0] Figure 37: MULT18X18SIO Primitive CEB CLK RSTB BCIN[17:0] CEB B[17:0] CLK RSTB DS312-2 (v3.8) August 26, 2009 Product Specification Cascading Multipliers The MULT18X18SIO primitive has two additional ports ...
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Functional Description The BCIN and BCOUT ports have associated dedicated routing that connects adjacent multipliers within the same column. Via the cascade connection, the BCOUT port of one multiplier block drives the BCIN port of the multiplier block directly above ...
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R Table 27 defines each port of the MULT18X18SIO primitive. Table 27: MULT18X18SIO Embedded Multiplier Primitives Description Signal Name Direction A[17:0] Input B[17:0] Input BCIN[17:0] Input P[35:0] Output BCOUT[17:0] Output CEA Input RSTA Input CEB Input RSTB Input CEP Input ...
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... The XC3S100E FPGA has two DCMs, one at the top and one at the bottom of the device. The XC3S250E and XC3S500E FPGAs each include four DCMs, two at the top and two at the bottom. The XC3S1200E and XC3S1600E FPGAs contain eight DCMs with two on each edge (see also Figure 45) ...
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R CLKIN CLKFB RST Table 28: DLL Signals Signal Direction CLKIN Input CLKFB Input CLK0 Output CLK90 Output CLK180 Output CLK270 Output CLK2X Output CLK2X180 Output CLKDV Output Delay-Locked Loop (DLL) The most basic function of the DLL component is ...
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... GCLK inputs that feed the DCM’s CLKIN input, as shown in provides the specific pin numbers by package for each GCLK input. The two additional DCM’s on the XC3S1200E and XC3S1600E have similar optimal connections from the left-edge LHCLK and the right-edge RHCLK inputs, as ...
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... GCLK7 GCLK6 GCLK5 Top Right DCM XC3S100: DCM_X0Y1 XC3S250E, XC3S500E: DCM_X1Y1 XC3S1200E, XC3S1600E: DCM_X2Y3 E 41) A Bottom Right DCM XC3S100: DCM_X0Y0 XC3S250E, XC3S500E: DCM_X1Y0 XC3S1200E, XC3S1600E: DCM_X2Y0 GCLK0 GCLK1 GCLK2 Differential Pair Differential Pair Pin Number for Single-Ended Input P38 P39 P40 ...
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... P16 N P12 G1 P17 P P15 G3 P20 N P16 H1 P21 P P17 H2 P22 N P18 H3 P23 Table 32: Direct Clock Input and Optional External Feedback to Right-Edge DCMs (XC3S1200E and XC3S1600E) Right Edge DCM/BUFGMUX RHCLK D BUFGMUX_X3Y5 C BUFGMUX_X3Y4 RHCLK7 RHCLK6 DCM_X3Y2 RHCLK5 RHCLK4 B BUFGMUX_X3Y3 A BUFGMUX_X3Y2 ...
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R Every FPGA input provides a possible DCM clock input, but the path is not temperature and voltage compensated like the GCLKs. Alternatively, clock signals within the FPGA optionally provide a DCM clock input via a Global Clock Multiplexer Buffer ...
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Functional Description Accommodating Input Frequencies Beyond Spec- ified Maximums If the CLKIN input frequency exceeds the maximum permit- ted, divide it down to an acceptable value using the CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to “TRUE”, the CLKIN frequency ...
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R The CLKFX_DIVIDE is an integer ranging from 1 to 32, inclusive and forms the denominator in example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the frequency of the output clock signal is 5/3 that of the input clock ...
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Functional Description FIXED Phase Shift Mode The FIXED phase shift mode shifts the DCM outputs by a fixed amount (T ), controlled by the user-specified PS PHASE_SHIFT attribute. The PHASE_SHIFT value (shown Figure 44) must be an ...
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R VARIABLE Phase Shift Mode In VARIABLE phase shift mode, the FPGA application dynamically adjusts the fine phase shift value using three Table 36: Signals for Variable Phase Mode Signal Direction (1) PSEN Input (1) PSCLK Input (1) PSINCDEC Input ...
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Functional Description Status Logic The Status Logic indicates the present state of the DCM and a means to reset the DCM to its initial known state. The Status Logic signals are described in In general, the Reset (RST) input is ...
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... I1 of the adjacent BUFGMUX. The clock switch matrix for the left- and right-edge BUFG- MUX elements receive signals from any of the three follow- ing sources: an LHCLK or RHCLK pin as appropriate, a Double-Line interconnect DCM in the XC3S1200E and XC3S1600E devices. www.xilinx.com Functional Description Figure ...
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... Number of DCMs and locations of these DCM varies for different device densities. The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right and one on the bottom right of the die. 3. See Figure 47a, which shows how the eight clock lines are multiplexed on the left-hand side of the device ...
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R By contrast, the clock switch matrixes on the top and bottom edges receive signals from any of the five following sources: two GCLK pins, two DCM outputs, or one Double-Line inter- connect. Table 41 indicates permissible connections between clock ...
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... Functional Description CLK Switch LHCLK or RHCLK input Double Line DCM output* *(XC3S1200E and XC3S1600E only) Figure 46: Clock Switch Matrix to BUFGMUX Pair Connectivity Quadrant Clock Routing The clock routing within the FPGA is quadrant-based, as shown in Figure 45. Each clock quadrant supports eight total clock signals, labeled ‘A’ through ‘H’ in Figure 47 ...
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R BUFGMUX Output X1Y10 (Global) X0Y9 (Left Half) X1Y11 (Global) X0Y8 (Left Half) X2Y10 (Global) X0Y7 (Left Half) X2Y11 (Global) X0Y6 (Left Half) X1Y0 (Global) X0Y5 (Left Half) X1Y1 (Global) X0Y4 (Left Half) X2Y0 (Global) X0Y3 (Left Half) X2Y1 (Global) ...
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Functional Description Interconnect For additional information, refer to the Using Interconnect chapter in UG331. Interconnect is the programmable network of signal path- ways between the inputs and outputs of functional elements within the FPGA, such as IOBs, CLBs, DCMs, and ...
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R Switch IOB Matrix Switch IOB Matrix Switch IOB Matrix Switch IOB Matrix Switch IOB Matrix Figure 49: Array of Interconnect Tiles in Spartan-3E FPGA Horizontal and Vertical Long Lines (horizontal channel shown as an example) CLB Horizontal and Vertical ...
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Functional Description Direct Connections Figure 50: Interconnect Types between Two Adjacent Interconnect Tiles (Continued) The four types of general-purpose interconnect available in each channel, shown in Figure 50, are described below. Long Lines Each set of 24 long line signals ...
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R Configuration For additional information on configuration, refer to UG332: Spartan-3 Generation Configuration User Guide. Differences from Spartan-3 FPGAs In general, Spartan-3E FPGA configuration modes are a superset to those available in Spartan-3 FPGAs. Two new modes added in Spartan-3E ...
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... Table 45: Number of Bits to Program a Spartan-3E FPGA (Uncompressed Bitstreams) Spartan-3E FPGA Configuration Bits XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Pin Behavior During Configuration For additional information, refer to the “Configuration Pins and Behavior during Configuration” chapter in UG332. Table 46: Pin Behavior during Configuration Pin Name ...
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R Table 46: Pin Behavior during Configuration (Continued) Pin Name Master Serial D1 D0/DIN DIN RDWR_B A23 A22 A21 A20 A19/VS2 A18/VS1 A17/VS0 A16 A15 A14 A13 A12 A11 A10 ...
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Functional Description JTAG boundary-scan pins: TDI, TDO, TMS, and TCK. All other configuration pins are dual-purpose I/O pins and are available to the FPGA application after the DONE pin goes High. See Start-Up for additional information. Table 47 shows the ...
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R Table 49: Pull-up or Pull-down Values for HSWAP, M[2:0], and VS[2:0] I/O Pull-up Resistors HSWAP Value during Configuration 0 Enabled 1 Disabled The Configuration section provides detailed schematics for each configuration mode. The schematics indicate the required logic values ...
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Functional Description Master Serial Mode For additional information, refer to the Master Serial Mode chapter in UG332. In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E FPGA configures itself from an attached Xilinx Platform P HSWAP Serial Master Mode ‘0’ ...
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R Table 50: Serial Master Mode Connections FPGA Pin Name Direction HSWAP Input User I/O Pull-Up Control. When Low during configuration, enables pull-up resistors in all P I/O pins to respective I/O bank V 0: Pull-ups during configuration 1: No ...
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... Configuration FPGA Bits XC3S100E 581,344 XC3S250E 1,353,728 XC3S500E 2,270,208 XC3S1200E 3,841,184 5,969,696 XC3S1600E 74 The XC3S1600E requires an 8 Mbit PROM. Two solutions are possible: either a single 8 Mbit XCF08P parallel/serial PROM or two 4 Mbit XCF04S serial PROMs cascaded. The two XCF04S PROMs use a 3.3V V XCF08P requires a 1 ...
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R +1.2V VCCINT P HSWAP VCCO_0 VCCO_2 DIN Serial Master Mode CCLK ‘0’ M2 DOUT ‘0’ M1 INIT_B ‘0’ M0 Spartan-3E FPGA +2.5V JTAG VCCAUX TDI TDI TDO TMS TMS TCK TCK TDO PROG_B DONE GND PROG_B Recommend open-drain driver ...
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Functional Description SPI Mode Variant Select S +2.5V JTAG TDI TMS TCK TDO PROG_B Recommend open-drain driver Figure 53: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B) Commands S Although SPI is a standard four-wire interface, ...
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R P HSWAP SPI Mode ‘0’ M2 ‘0’ M1 ‘1’ M0 Spartan-3E Variant Select ‘1’ VS2 ‘1’ VS1 ‘0’ VS0 +2.5V JTAG TDI TDI TMS TMS TCK TCK TDO PROG_B PROG_B Recommend open-drain driver Figure 54: Atmel SPI-based DataFlash Configuration ...
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Functional Description Table 53: Variant Select Codes for Various SPI Serial Flash PROMs SPI Read VS2 VS1 VS0 Command FAST READ (0x0B (see Figure 53) READ (0x03 (see Figure 53) READ ARRAY (0xE8) 1 ...
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R W Table 54 shows the connections between the SPI Flash PROM and the FPGA’s SPI configuration interface. Each SPI Flash PROM vendor uses slightly different signal nam- ing. The SPI Flash PROM’s write protect and hold controls Table 54: ...
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Functional Description Table 55: Serial Peripheral Interface (SPI) Connections FPGA Pin Name Direction Input User I/O Pull-Up Control. When Low HSWAP during configuration, enables pull-up P resistors in all I/O pins to respective I/O bank V CCO 0: Pull-ups during ...
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R Table 55: Serial Peripheral Interface (SPI) Connections (Continued) FPGA Pin Name Direction Open-drain FPGA Configuration Done. Low during DONE bidirectional configuration. Goes High when FPGA I/O successfully completes configuration. Requires external 330 Ω pull-up resistor to 2.5V. Input Program ...
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... FPGA and Smallest SPI Flash PROM Device XC3S100E , POR XC3S250E XC3S500E XC3S1200E XC3S1600E CCLK Frequency In SPI Flash mode, the FPGA’s internal oscillator generates the configuration clock frequency. The FPGA provides this clock on its CCLK output pin, driving the PROM’s clock input Figure 54 ...
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R If not using the SPI Flash PROM after configuration, drive CSO_B High to disable the PROM. The MOSI, DIN, and CCLK pins are then available to the FPGA application. Because all the interface pins are user I/O after configura- ...
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Functional Description Daisy-Chaining If the application requires multiple FPGAs with different con- figurations, then configure the FPGAs using a daisy chain, as shown in Figure 57. Daisy-chaining from a single SPI serial Flash PROM is supported in Stepping 1 devices. ...
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R Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode For additional information, refer to the “Master BPI Mode” chapter in UG332. In Byte-wide Peripheral Interface (M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA config- ures itself from an industry-standard parallel NOR ...
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Functional Description Not available in VQ100 package BPI Mode +2.5V JTAG TDI TMS TCK TDO PROG_B Recommend open-drain driver Figure 58: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs A During configuration, the value of the M0 ...
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R This addressing flexibility allows the FPGA to share the par- allel Flash PROM with an external or embedded processor. Depending on the specific processor architecture, the pro- cessor boots either from the top or bottom of memory. The FPGA ...
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Functional Description Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Continued) Pin Name FPGA Direction LDC1 Output PROM Output Enable HDC Output PROM Write Enable LDC2 Output PROM Byte Mode D A[23:0] Output Address D[7:0] Input Data Input CSO_B Output Chip ...
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R Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Continued) Pin Name FPGA Direction CCLK Output Configuration Clock. Generated by FPGA internal oscillator. Frequency controlled by ConfigRate bitstream generator option. If CCLK PCB trace is long or has multiple connections, terminate ...
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... Table 60: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM Uncompressed Spartan-3E FPGA File Sizes (bits) XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Compatible Flash Families The Spartan-3E BPI configuration interface operates with a wide variety x8/x16 parallel NOR Flash devices. Table 61 provides a few Flash memory families that operate with the Spartan-3E BPI interface ...
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R desired, use a larger parallel Flash PROM to contain addi- tional non-volatile application data, such as MicroBlaze pro- cessor code, or other user data, such as serial numbers and Ethernet MAC IDs. In such an example, the FPGA config- ...
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Functional Description Table 63: FPGA Connections to Flash PROM with IO15/A-1 Pin (Continued) Connection to Flash PROM with FPGA Pin IO15/A-1 Pin A[23:1] A[n:0] A0 IO15/A-1 D[7:0] IO[7:0] User I/O Upper data lines IO[14:8] not required unless used as x16 ...
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R Stepping 0 Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration The FPGA can always be reprogrammed via the JTAG port, regardless of the mode pin (M[2:0]) settings. However, Stepping 0 devices have a minor limitation. If ...
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Functional Description After the FPGA configures itself using BPI mode from one end of the parallel Flash PROM, then the FPGA can trigger a MultiBoot event and reconfigure itself from the opposite end of the parallel Flash PROM. MultiBoot is ...
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R Intelligent Download Host VCC Configuration Memory Source READ/WRITE - Internal memory - Disk drive - Over network - Over RF link GND - Microcontroller - Processor - Tester - Computer PROG_B Recommend open-drain driver Slave Parallel Mode For additional ...
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Functional Description can also be eliminated from the interface. However, RDWR_B must remain Low during configuration. After configuration, all of the interface pins except DONE and PROG_B are available as user I/Os. Alternatively, the bidirectional SelectMAP configuration interface is available ...
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R Table 65: Slave Parallel Mode Connections (Continued) Pin Name FPGA Direction INIT_B Open-drain Initialization Indicator. Active Low. bidirectional I/O Goes Low at the start of configuration during the Initialization memory clearing process. Released at the end of memory clearing, ...
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Functional Description Parallel V Intelligent Download Host VCC DATA[7:0] Configuration BUSY Memory Source SELECT READ/WRITE • Internal memory CLOCK • Disk drive • PROG_B Over network • DONE Over RF link INIT_B GND • Microcontroller • Processor • Tester PROG_B ...
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R V Intelligent Download Host VCC Configuration CLOCK Memory Source SERIAL_OUT PROG_B • Internal memory DONE • Disk drive INIT_B • Over network • Over RF link GND • Microcontroller • Processor • Tester • Computer PROG_B Recommend open-drain driver ...
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Functional Description Table 66: Slave Serial Mode Connections Pin Name FPGA Direction HSWAP Input User I/O Pull-Up Control. When Low during configuration, enables pull-up resistors in all I/O pins to respective I/O bank 0: Pull-up during configuration 1: No pull-ups ...
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R Intelligent V Download Host VCC Configuration CLOCK Memory Source SERIAL_OUT PROG_B • Internal memory DONE • Disk drive • INIT_B Over network • Over RF link GND • Microcontroller • Processor • Tester • Computer PROG_B Recommend open-drain driver ...
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... Table 67: Spartan-3E JTAG Device Identifiers 4-Bit Revision Code Spartan-3E FPGA Step 0 Step 1 XC3S100E 0x0 0x1 XC3S250E 0x0 0x1 0x0 XC3S500E 0x4 0x2 0x0 XC3S1200E 0x2 0x1 0x0 XC3S1600E 0x2 0x1 102 +1.2V P VCCO_0 VCCO_0 VCCO_2 VCCO_2 JTAG Mode ‘1’ FPGA ‘ ...
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R Maximum Bitstream Size for Daisy-Chains The maximum bitstream length supported by Spartan-3E FPGAs in serial daisy-chains is 4,294,967,264 bits (4 Gbits), roughly equivalent to a daisy-chain with 720 XC3S1600E FPGAs. This is a limit only for serial daisy-chains where ...
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Functional Description Figure 66: Generalized Spartan-3E FPGA Configuration Logic Block Diagram 104 www.xilinx.com R DS312-2_57_102605 DS312-2 (v3.8) August 26, 2009 Product Specification ...
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R DS312-2 (v3.8) August 26, 2009 Product Specification Set PROG_B Low Power-On after Power-On V >1V CCINT No and V > 2V CCAUX and V Bank 2 > 1V CCO Yes Yes Clear configuration PROG_B = Low memory No INIT_ ...
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Functional Description Load JPROG instruction Figure 68: Boundary-Scan Configuration Flow Diagram 106 Set PROG_B Low Power-On after Power-On V >1V CCINT and V > CCAUX and V Bank 2 > 1V CCO Yes Clear Yes configuration PROG_B = ...
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R Start-Up At the end of configuration, the FPGA automatically pulses the Global Set/Reset (GSR) signal, placing all flip-flops in a known state. After configuration completes, the FPGA switches over to the user application loaded into the FPGA. The sequence ...
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... FPGA families. The Readback feature is available in most Spartan-3E FPGA product options, as indicated in back feature is not available in the XC3S1200E and XC3S1600E FPGAs when using the -4 speed grade in the Commercial temperature grade. Similarly, block RAM Read- back support is not available in the -4 speed grade, Com- mercial temperature devices ...
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R Bitstream Generator (BitGen) Options For additional information, refer to the “Configuration Bit- stream Generator (BitGen) Settings” chapter in UG332. Various Spartan-3E FPGA functions are controlled by spe- cific bits in the configuration bitstream image. These values Table 69: Spartan-3E ...
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Functional Description Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued) Pins/Function Values Option Name Affected (default) DonePin DONE pin Pullup Pullnone DriveDone DONE pin DonePipe DONE pin ProgPin PROG_B pin Pullup Pullnone TckPin JTAG TCK pin Pullup Pulldown Pullnone ...
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R Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued) Pins/Function Values Option Name Affected (default) CRC Configuration Enable Disable Persist SelectMAP interface pins, BPI mode, Slave mode, Configuration Powering Spartan-3E FPGAs For additional information, refer to the “Powering Spartan-3 ...
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Functional Description Voltage Regulators Various power supply manufacturers offer complete power solutions for Xilinx FPGAs including some with integrated three-rail regulators specifically designed for Spartan-3 and Spartan-3E FPGAs. The Xilinx Power Corner vides links to vendor solution guides and Xilinx ...
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... Stepping 0 devices and Stepping 1 devices. Stepping 0 Production from 2005 to 2007 -4C only Different revision fields. See 90 MHz (200 MHz for XC3S1200E) Split ranges at 5 – 90 MHz and 220 – 307 MHz (single range 5 – 307 MHz for XC3S1200E) No, single FPGA only ...
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Functional Description Software Version Requirements Production Spartan-3E applications must be processed using the Xilinx ISE 8.1i, Service Pack 3 or later develop- ment software, using the v1.21 or later speed files. The ISE 8.1i software implements critical bitstream generator updates. ...
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... BPI Mode Interaction with Right and Bottom Edge Global Clock Inputs section. Added Production Stepping FIXED Phase Shift Mode and DLL Clock Input Connections 45. Added additional information on HSWAP behavior to Table 46. Updated bitstream image sizes for the XC3S1200E and XC3S1600E 45, Table 51, Table 57, and Table 54. Updated Figure 56 ...
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Functional Description Date Version 05/30/06 3.2.1 Corrected various typos and incorrect links. 10/02/06 3.3 Clarified that the block RAM the Industrial temperature range. 11/09/06 3.4 Updated the description of the Alignment is no longer supported. Updated input voltage tolerance. Replaced ...
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R DS312-3 (v3.8) August 26, 2009 DC Electrical Characteristics In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the ...
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DC and Switching Characteristics Power Supply Specifications Table 74: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes ...
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R General Recommended Operating Conditions Table 77: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX (2,3,4,5) V Input voltage extremes to avoid ...
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DC and Switching Characteristics General DC Characteristics for I/O Pins Table 78: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description I Leakage current at User I/O, L Input-only, Dual-Purpose, and Dedicated pins (2) I Current through ...
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... XC3S1600E 65 XC3S100E 0.8 XC3S250E 0.8 XC3S500E 0.8 XC3S1200E 1.5 XC3S1600E 1.5 XC3S100E 8 XC3S250E 12 XC3S500E 18 XC3S1200E 35 XC3S1600E 45 Table 77. of 25° 2.625V. The FPGA is programmed with a “blank” configuration data file (i.e., a CCAUX www.xilinx.com DC and Switching Characteristics Commercial Industrial (2) (2) Maximum Maximum Units ...
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DC and Switching Characteristics Single-Ended I/O Standards Table 80: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V for Drivers CCO IOSTANDARD Attribute Min (V) Nom (V) LVTTL 3.0 (4) LVCMOS33 3.0 (4,5) LVCMOS25 2.3 LVCMOS18 1.65 LVCMOS15 1.4 ...
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R Table 81: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions IOSTANDARD Attribute (mA) (mA) (3) LVTTL 2 2 – – – – – ...
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DC and Switching Characteristics Differential I/O Standards Internal Logic V V GND level Table 82: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO IOSTANDARD Attribute Min (V) LVDS_25 2.375 BLVDS_25 2.375 MINI_LVDS_25 2.375 (2) LVPECL_25 RSDS_25 ...
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R Internal Logic V OUTN V OUTP GND level Table 83: DC Characteristics of User I/Os Using Differential Signal Standards V OD IOSTANDARD Min Typ Attribute (mV) (mV) LVDS_25 250 350 BLVDS_25 250 350 MINI_LVDS_25 300 – RSDS_25 100 – ...
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... Xilinx development software) and back-annotated to the simulation netlist. Table 84: Spartan-3E v1.27 Speed Grade Designations Device Advance XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Table 85 provides the history of the Spartan-3E speed files since all devices reached Production status. Table 85: Spartan-3E Speed File Version History ISE Version Release 1 ...
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... Fast slew rate, (3) with DCM XC3S500E XC3S1200E XC3S1600E (2) LVCMOS25 , XC3S100E 12 mA output drive, XC3S250E Fast slew rate, without DCM XC3S500E XC3S1200E XC3S1600E Table 95 and are based on the operating conditions set forth in Table www.xilinx.com Speed Grade -5 -4 Max Max Units 2.66 2. ...
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... IFD_DELAY_VALUE = 0, XC3S250E (4) with DCM XC3S500E XC3S1200E XC3S1600E (3) LVCMOS25 , 2 XC3S100E IFD_DELAY_VALUE = 3 XC3S250E default software setting 3 XC3S500E 3 XC3S1200E 3 XC3S1600E Table 95 and are based on the operating conditions set forth in Table Table www.xilinx.com Speed Grade -5 -4 Device Min Min 2.65 2.98 2.25 2.59 2.25 2.59 2 ...
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R Table 88: Setup and Hold Times for the IOB Input Path Symbol Description Setup Times T Time from the setup of data at the IOPICK Input pin to the active transition at the ICLK input of the Input Flip-Flop ...
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DC and Switching Characteristics Table 90: Propagation Times for the IOB Input Path Symbol Description Propagation Times T The time it takes for data to IOPLI travel from the Input pin through the IFF latch to the I output with ...
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R Table 92: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output Flip-Flop IOCKP (OFF), the time from the active transition at the OCLK input to data appearing at the Output pin Propagation ...
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DC and Switching Characteristics Table 93: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at the OTCLK IOCKHZ input of the Three-state Flip-Flop (TFF) to when the Output pin enters ...
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R Table 94: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow ...
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DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test condi- tions. Table 95 lists the conditions to use for each standard. The method for measuring Input timing ...
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R Table 95: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V REF DIFF_SSTL18_I - DIFF_SSTL2_I - Notes: 1. Descriptions of the relevant symbols are as follows: V – The reference voltage for setting the input switching ...
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... Device VQ100 CP132 XC3S100E 2 XC3S250E 2 XC3S500E 2 XC3S1200E - XC3S1600E - 136 equivalent number of pairs is based on characterization and might not match the physical number of pairs. For each out- put signal standard and drive strength, mends the maximum number of SSOs, switching in the same direction, allowed per V bank ...
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R Table 97: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO Package Type Signal Standard VQ TQ (IOSTANDARD) 100 144 Single-Ended Standards LVTTL Slow ...
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DC and Switching Characteristics Configurable Logic Block (CLB) Timing Table 98: CLB (SLICEM) Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, CKO the time from the active transition at the CLK input to data appearing at ...
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R Table 99: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data SHCKO appearing on the distributed RAM output Setup Times T Setup time of data at the BX ...
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DC and Switching Characteristics Clock Buffer/Multiplexer Switching Characteristics Table 101: Clock Distribution Switching Characteristics Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as ...
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Embedded Multiplier Timing Table 102 Embedded Multiplier Timing Symbol Combinatorial Delay T Combinatorial multiplier propagation delay from the A and B MULT inputs to the P outputs, assuming 18-bit inputs and a 36-bit ...
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DC and Switching Characteristics Block RAM Timing Table 103: Block RAM Timing Symbol Clock-to-Output Times T When reading from block RAM, the delay from the BCKO active transition at the CLK input to data appearing at the DOUT output Setup ...
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... FPGA logic. See XAPP469, Spread-Spectrum Clocking Reception for Displays for details. Description Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E (3) XC3S1200E Stepping 1 All F < 150 MHz CLKIN F > 150 MHz CLKIN (4) F < 150 MHz ...
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... All Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E XC3S1200E Stepping 1 All Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E XC3S1200E Stepping 1 All Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E XC3S1200E Stepping 1 All All All www.xilinx.com Speed Grade -5 -4 Min Max Min Max Units N/A N MHz 200 MHz 5 275 ...
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R Table 105: Switching Characteristics for the DLL (Continued) Symbol (4) Phase Alignment CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB inputs CLKOUT_PHASE_DLL Phase offset between DLL outputs Lock Time (3) LOCK_DLL When using the DLL alone: The time from ...
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... DLL CLK0 output when both the DFS and DLL are used 146 Description F < 150 MHz CLKFX F > 150 MHz CLKFX Description Stepping 0 XC3S100E XC3S250E XC3S500E XC3S1600E Stepping 0 XC3S1200E Stepping 1 CLKIN ≤ 20 MHz CLKIN > 20 MHz www.xilinx.com Speed Grade -5 -4 Min Max Min Max (4) ...
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R Table 107: Switching Characteristics for the DFS (Continued) Symbol Lock Time (2) LOCK_FX The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 ...
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DC and Switching Characteristics Table 109: Switching Characteristics for the PS in Variable Phase Mode (Continued) Symbol Notes: 1. The numbers in this table are based on the operating conditions set forth in 2. The maximum variable phase shift range, ...
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R Miscellaneous DCM Timing Table 110: Miscellaneous DCM Timing Symbol (1) DCM_RST_PW_MIN Minimum duration of a RST pulse width (2) DCM_RST_PW_MAX Maximum duration of a RST pulse width (3) DCM_CONFIG_LAG_TIME Maximum duration from V configuration successfully completed (DONE pin goes ...
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... All Speed Grades Device Min Max XC3S100E - 5 XC3S250E - 5 XC3S500E - 5 XC3S1200E - 5 XC3S1600E - 7 All 0.5 - XC3S100E - 0.5 XC3S250E - 0.5 XC3S500E - 1 XC3S1200E - 2 XC3S1600E - 2 All 250 - All 0.5 4.0 77. This means power must be applied to all V DS312-3 (v3.8) August 26, 2009 Product Specification R 1.2V 2.5V Units μ μ ...
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R Configuration Clock (CCLK) Characteristics Table 112: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol Description CCLK clock period by T ConfigRate setting CCLK1 T CCLK3 T CCLK6 T CCLK12 T CCLK25 T CCLK50 Notes: 1. Set the ...
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DC and Switching Characteristics Table 115: Slave Mode CCLK Input Low and High Time Symbol T CCLK Low and High time SCCL, T SCCH 152 Description www.xilinx.com R Min Max Units ∞ DS312-3 (v3.8) August 26, 2009 Product ...
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R Master Serial and Slave Serial Mode Timing PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 75: Waveforms for Master Serial and Slave Serial Configuration Table 116: Timing for the Master Serial and Slave Serial Configuration Modes ...
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DC and Switching Characteristics Slave Parallel Mode Timing PROG_B (Input) INIT_B (Open-Drain) CSI_B (Input) RDWR_B (Input) CCLK (Input (Inputs) High-Z BUSY (Output) Notes possible to abort configuration by pulling CSI_B Low in a given ...
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R Table 117: Timing for the Slave Parallel Configuration Mode (Continued) Symbol Hold Times T The time from the active edge of the CCLK pin to the point when data is last SMCCD held at the D0-D7 pins T The ...
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DC and Switching Characteristics Serial Peripheral Interface (SPI) Configuration Timing PROG_B (Input) HSWAP HSWAP must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) M[2:0] <0:0:1> (Input) T MINIT INIT_B (Open-Drain) CCLK DIN ...
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R Table 119: Configuration Timing Requirements for Attached SPI Serial Flash Symbol T SPI serial Flash PROM chip-select time CCS T SPI serial Flash PROM data input setup time DSU T SPI serial Flash PROM data input hold time DH ...
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DC and Switching Characteristics Byte Peripheral Interface (BPI) Configuration Timing PROG_B (Input) HSWAP HSWAP must be stable before INIT_B goes High and constant throughout the configuration process. (Input) M[2:0] <0:1:0> (Input) T MINIT INIT_B (Open-Drain) LDC[2:0] HDC CSO_B CCLK A[23:0] ...
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R Table 121: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol Description T Parallel NOR Flash PROM chip-select time ELQV T Parallel NOR Flash PROM output-enable time GLQV T Parallel NOR Flash PROM ...
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DC and Switching Characteristics IEEE 1149.1/1553 JTAG Test Access Port Timing TCK (Input) TMS (Input) TDI (Input) TDO (Output) Table 123: Timing for the JTAG Test Access Port Symbol Clock-to-Output Times T The time from the falling transition on the ...
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... Table 106, and Table 107. Added minimum INIT_B pulse width specification Table 111. Increased data hold time for Slave Parallel mode to 1 117. Improved the DCM performance for the XC3S1200E, Stepping 0 in 105, Table 106, and Table 107. Corrected links in Table 122 ...
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DC and Switching Characteristics Date Version 04/18/08 3.7 Clarified that Stepping 0 was offered only for -4C and removed Stepping 0 -5 specifications. Added reference to XAPP459 in to 3.465V (3.3V + 5%) in Updated Recommended Operating Conditions for LVCMOS ...
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R DS312-4 (v3.8) August 26, 2009 Introduction This section describes the various pins on a Spartan®-3E FPGA and how they connect within the supported compo- nent packages. Table 124: Types of Pins on Spartan-3E FPGAs Type / Color Code I/O ...
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Pinout Descriptions Table 124: Types of Pins on Spartan-3E FPGAs (Continued) Type / Color Code CONFIG Dedicated configuration pin. Not available as a user-I/O pin. Every package has two dedicated configuration pins. These pins are powered by VCCAUX. See the ...
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R Package Overview Table 125 shows the eight low-cost, space-saving produc- tion package styles for the Spartan-3E family. Each pack- age style is available as a standard and an environmentally friendly lead-free (Pb-free) option. The Pb-free packages include an extra ...
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Pinout Descriptions Mechanical Drawings Detailed mechanical drawings for each package type are available from the Xilinx® web site at the specified location in Table 127. Table 127: Xilinx Package Mechanical Drawings and Material Declaration Data Sheets Package VQ100 VQG100 CP132 ...
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... XC3S500E FT256 190 XC3S1200E 190 XC3S500E 232 XC3S1200E FG320 250 XC3S1600E 250 XC3S1200E 304 FG400 XC3S1600E 304 XC3S1600E FG484 376 Notes: 1. Some VREF pins are on INPUT pins. See pinout tables for details. 2. All devices have 24 possible global clock and right- and left-half side clock inputs. The right-half and bottom-edge clock pins have shared functionality in some FPGA configuration modes ...
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... XC3S250E XC3S500E XC3S1200E FG320 XC3S500E XC3S1200E XC3S1600E FG400 XC3S1200E XC3S1600E FG484 XC3S1600E 168 age body (case) and the die junction temperature per watt of power consumption. The junction-to-board (θ similarly reports the difference between the board and junc- tion temperature. The junction-to-ambient (θ ...
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R VQ100: 100-lead Very-thin Quad Flat Package The XC3S100E, XC3S250E, and the XC3S500E devices are available in the 100-lead very-thin quad flat package, VQ100. All devices share a common footprint for this pack- age as shown in Table 131 and ...
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Pinout Descriptions Table 131: VQ100 Package Pinout (Continued) XC3S100E XC3S250E XC3S500E Bank Pin Name 3 IO_L02N_3/VREF_3 3 IO_L02P_3 3 IO_L03N_3/LHCLK1 3 IO_L03P_3/LHCLK0 3 IO_L04N_3/LHCLK3 3 IO_L04P_3/LHCLK2 3 IO_L05N_3/LHCLK5 3 IO_L05P_3/LHCLK4 3 IO_L06N_3/LHCLK7 3 IO_L06P_3/LHCLK6 3 IO_L07N_3 3 IO_L07P_3 3 IP ...
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R User I/Os by Bank Table 132 indicates how the 66 available user-I/O pins are distributed between the four I/O banks on the VQ100 pack- age. Table 132: User I/Os Per Bank for XC3S100E, XC3S250E, and XC3S500E in the VQ100 ...
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Pinout Descriptions VQ100 Footprint In Figure 81, note pin 1 indicator in top-left corner and logo orientation. PROG_B 1 IO_L01P_3 2 IO_L01N_3 3 IO_L02P_3 4 IO_L02N_3/VREF_3 5 VCCINT 6 GND 7 VCCO_3 8 IO_L03P_3/LHCLK0 9 IO_L03N_3/LHCLK1 10 IO_L04P_3/LHCLK2 11 IO_L04N_3/LHCLK3 ...
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R CP132: 132-ball Chip-scale Package The XC3S100E, XC3S250E and the XC3S500E FPGAs are available in the 132-ball chip-scale package, CP132. The devices share a common footprint for this package as shown in Table 133 and Figure 82. Table 133 lists ...
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Pinout Descriptions Table 133: CP132 Package Pinout (Continued) XC3S100E Bank Pin Name 0 VCCO_0 0 VCCO_0 1 IO/A0 1 IO/VREF_1 1 IO_L01N_1/A15 1 IO_L01P_1/A16 1 IO_L02N_1/A13 1 IO_L02P_1/A14 1 IO_L03N_1/A11 1 IO_L03P_1/A12 1 IO_L04N_1/A9/RHCLK1 1 IO_L04P_1/A10/RHCLK0 1 IO_L05N_1/A7/RHCLK3/TRDY1 1 IO_L05P_1/A8/RHCLK2 ...
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R Table 133: CP132 Package Pinout (Continued) XC3S100E Bank Pin Name 2 IO_L06P_2/D2/GCLK2 2 IO_L07N_2/DIN/D0 2 IO_L07P_2/ IO_L10N_2/VS1/A18 2 IO_L10P_2/VS2/A19 2 IO_L11N_2/CCLK 2 ...
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Pinout Descriptions Table 133: CP132 Package Pinout (Continued) XC3S100E Bank Pin Name 3 IO_L09P_3 3 IP/VREF_3 3 VCCO_3 3 VCCO_3 GND N.C. (GND) GND GND GND N.C. (GND) GND GND GND GND GND GND GND GND GND GND GND GND ...
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R User I/Os by Bank Table 134 shows how the 83 available user-I/O pins are dis- tributed on the XC3S100E FPGA packaged in the CP132 package. Table 135 indicates how the 92 available user-I/O Table 134: User I/Os Per Bank ...
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Pinout Descriptions Footprint Migration Differences Table 136 summarizes any footprint and functionality differ- ences between the XC3S100E, the XC3S250E, and the XC3S500E FPGAs that may affect easy migration between devices in the CP132 package. There are 14 such balls. All ...
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R CP132 Footprint I/O A PROG_B TDI GND L11P_0 I/O I/O I/O I/O B L11N_0 L10P_0 L01N_3 L01P_3 HSWAP I/O I/O I/O C GND L10N_0 L02N_3 L02P_3 I/O I/O D VCCINT L03N_3 L03P_3 INPUT E VCCO_3 GND ...
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Pinout Descriptions TQ144: 144-lead Thin Quad Flat Package The XC3S100E and the XC3S250E FPGAs are available in the 144-lead thin quad flat package, TQ144. Both devices share a common footprint for this package as shown in Table 137 and Figure ...
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R Table 137: TQ144 Package Pinout (Continued) Bank XC3S100E Pin Name 1 IO_L01P_1/A16 1 IO_L02N_1/A13 1 IO_L02P_1/A14 1 IO_L03N_1/A11 1 IO_L03P_1/A12 1 IO_L04N_1/A9/RHCLK1 1 IO_L04P_1/A10/RHCLK0 1 IO_L05N_1/A7/RHCLK3/TRDY1 1 IO_L05P_1/A8/RHCLK2 1 IO_L06N_1/A5/RHCLK5 1 IO_L06P_1/A6/RHCLK4/IRDY1 1 IO_L07N_1/A3/RHCLK7 1 IO_L07P_1/A4/RHCLK6 1 IO_L08N_1/A1 1 ...
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Pinout Descriptions Table 137: TQ144 Package Pinout (Continued) Bank XC3S100E Pin Name 2 IO_L08P_2/M0 2 IO_L09N_2/VS1/A18 2 IO_L09P_2/VS2/A19 2 IO_L10N_2/CCLK 2 IO_L10P_2/VS0/A17 IP_L03N_2/VREF_2 2 IP_L03P_2 2 IP_L06N_2/M2/GCLK1 2 IP_L06P_2/RDWR_B/GCLK0 2 VCCO_2 2 VCCO_2 ...
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R Table 137: TQ144 Package Pinout (Continued) Bank XC3S100E Pin Name IP/VREF_3 3 VCCO_3 3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Pinout Descriptions User I/Os by Bank Table 138 and Table 139 indicate how the 108 available user-I/O pins are distributed between the four I/O banks on the TQ144 package. Table 138: User I/Os Per Bank for the XC3S100E in the ...
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R TQ144 Footprint Note pin 1 indicator in top-left corner and logo orientation. Double arrows ( ) indicates a pinout migration difference between the XC3S100E and XC3S250E. PROG_B 1 IO_L01P_3 2 IO_L01N_3 3 IO_L02P_3 4 IO_L02N_3/VREF_3 IO_L03P_3 ...
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Pinout Descriptions PQ208: 208-pin Plastic Quad Flat Package The 208-pin plastic quad flat package, PQ208, supports two different Spartan-3E FPGAs, including the XC3S250E and the XC3S500E. Table 141 lists all the PQ208 package pins. They are sorted by bank number ...
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R Table 141: PQ208 Package Pinout (Continued) XC3S250E XC3S500E Bank Pin Name 1 IO_L13P_1 1 IO_L14N_1 1 IO_L14P_1 1 IO_L15N_1/LDC0 1 IO_L15P_1/HDC 1 IO_L16N_1/LDC2 1 IO_L16P_1/LDC1 ...
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Pinout Descriptions Table 141: PQ208 Package Pinout (Continued) XC3S250E XC3S500E Bank Pin Name 3 IO_L10N_3/LHCLK7 3 IO_L10P_3/LHCLK6 3 IO_L11N_3 3 IO_L11P_3 3 IO_L12N_3 3 IO_L12P_3 3 IO_L13N_3 3 IO_L13P_3 3 IO_L14N_3 3 IO_L14P_3 3 IO_L15N_3 3 IO_L15P_3 3 IO_L16N_3 3 ...
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R User I/Os by Bank Table 142 indicates how the 158 available user-I/O pins are distributed between the four I/O banks on the PQ208 pack- age. Table 142: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 ...
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Pinout Descriptions PQ208 Footprint (Left) PROG_B IO_L01P_3 IO_L01N_3 IO_L02P_3 IO_L02N_3/VREF_3 VCCAUX IO_L03P_3 IO_L03N_3 GND IO_L04P_3 11 IO_L04N_3 12 VCCINT IO_L05P_3 15 IO_L05N_3 16 GND IO_L06P_3 18 IO_L06N_3 19 IP/VREF_3 20 VCCO_3 21 IO_L07P_3/LHCLK0 IO_L07N_3/LHCLK1 IO_L08P_3/LHCLK2 IO_L08N_3/LHCLK3 GND IO_L09P_3/LHCLK4 IO_L09N_3/LHCLK5 IO_L10P_3/LHCLK6 ...
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R PQ208 Footprint (Right) DS312-4 (v3.8) August 26, 2009 Product Specification Bank 0 Bank 2 Figure 85: PQ208 Footprint (Right) www.xilinx.com Pinout Descriptions 156 GND 155 TMS 154 IP 153 IO_L16N_1/LDC2 152 IO_L16P_1/LDC1 151 IO_L15N_1/LDC0 150 IO_L15P_1/HDC 149 VCCAUX 148 ...
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... IO_L11N_0/GCLK11 0 IO_L11P_0/GCLK10 192 to a VREF pin on the XC3S500E and XC3S1200E FPGA. If the FPGA application uses an I/O standard that requires a VREF voltage reference, connect the highlighted pin to the VREF voltage supply, even though this does not actually connect to the XC3S250E FPGA. This VREF connection on the board allows future migration to the larger devices with- out modifying the printed-circuit board ...
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... VCCO_0 0 VCCO_0 0 VCCO_0 1 IO_L01N_1/A15 1 IO_L01P_1/A16 1 IO_L02N_1/A13 1 IO_L02P_1/A14 DS312-4 (v3.8) August 26, 2009 Product Specification XC3S500E Pin Name XC3S1200E Pin Name IO_L12N_0 IO_L12N_0 IO_L12P_0 IO_L12P_0 IO_L13N_0 IO_L13N_0 IO_L13P_0 IO_L13P_0 IO_L14N_0/VREF_0 IO_L14N_0/VREF_0 IO_L14P_0 IO_L14P_0 IO_L15N_0 IO_L15N_0 IO_L15P_0 IO_L15P_0 IO_L17N_0/VREF_0 IO_L17N_0/VREF_0 IO_L17P_0 IO_L17P_0 IO_L18N_0 ...
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... IO_L14P_1 1 IO_L15N_1 1 IO_L15P_1 1 IO_L16N_1 1 IO_L16P_1 IO_L18N_1/LDC0 1 IO_L18P_1/HDC 1 IO_L19N_1/LDC2 1 IO_L19P_1/LDC1 194 XC3S500E Pin Name XC3S1200E Pin Name IO_L04N_1/VREF_1 IO_L04N_1/VREF_1 IO_L04P_1 IO_L04P_1 IO_L05N_1 IO_L05N_1 IO_L05P_1 IO_L05P_1 IO_L06N_1 IO_L06N_1 IO_L06P_1 IO_L06P_1 IO_L07N_1/A11 IO_L07N_1/A11 IO_L07P_1/A12 IO_L07P_1/A12 IO_L08N_1/VREF_1 IO_L08N_1/VREF_1 IO_L08P_1 IO_L08P_1 IO_L09N_1/A9/RHCLK1 IO_L09N_1/A9/RHCLK1 IO_L09P_1/A10/RHCLK0 IO_L09P_1/A10/RHCLK0 ...
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... IP 2 IO/D5 2 IO/M1 2 IO/VREF_2 2 IO/VREF_2 2 IO_L01N_2/INIT_B 2 IO_L01P_2/CSO_B 2 IO_L03N_2/MOSI/CSI_B 2 IO_L03P_2/DOUT/BUSY 2 IO_L04N_2 2 IO_L04P_2 2 IO_L05N_2 2 IO_L05P_2 2 IO_L06N_2 2 IO_L06P_2 2 N. DS312-4 (v3.8) August 26, 2009 Product Specification XC3S500E Pin Name XC3S1200E Pin Name IP/VREF_1 IP/VREF_1 IP/VREF_1 IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IO/D5 ...
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... IP_L08N_2/VREF_2 2 IP_L08P_2 2 IP_L11N_2/M2/GCLK1 2 IP_L11P_2/RDWR_B/ GCLK0 2 IP_L17N_2 2 IP_L17P_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 196 XC3S500E Pin Name XC3S1200E Pin Name IO_L07P_2 IO_L07P_2 IO_L09N_2/D6/GCLK13 IO_L09N_2/D6/GCLK13 IO_L09P_2/D7/GCLK12 IO_L09P_2/D7/GCLK12 IO_L10N_2/D3/GCLK15 IO_L10N_2/D3/GCLK15 IO_L10P_2/D4/GCLK14 IO_L10P_2/D4/GCLK14 IO_L12N_2/D1/GCLK3 IO_L12N_2/D1/GCLK3 IO_L12P_2/D2/GCLK2 IO_L12P_2/D2/GCLK2 IO_L13N_2/DIN/D0 IO_L13N_2/DIN/D0 IO_L13P_2/M0 IO_L13P_2/M0 IO_L14N_2/VREF_2 IO_L14N_2/VREF_2 IO_L14P_2 IO_L14P_2 IO_L15N_2 ...
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... IO_L12P_3 3 IO_L13N_3 3 IO_L13P_3 IO_L15N_3 3 IO_L15P_3 3 IO_L16N_3 3 IO_L16P_3 DS312-4 (v3.8) August 26, 2009 Product Specification XC3S500E Pin Name XC3S1200E Pin Name IO_L01N_3 IO_L01N_3 IO_L01P_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L02P_3 IO_L03N_3 IO_L03N_3 IO_L03P_3 IO_L03P_3 IO_L04N_3/VREF_3 IO_L04N_3/VREF_3 IO_L04P_3 IO_L04P_3 IO_L05N_3 IO_L05N_3 IO_L05P_3 IO_L05P_3 IO_L06N_3 ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 198 XC3S500E Pin Name XC3S1200E Pin Name IO_L17N_3 IO_L17N_3 IO_L17P_3 IO_L17P_3 IO_L18N_3 IO_L18N_3 IO_L18P_3 IO_L18P_3 IO_L19N_3 IO_L19N_3 IO_L19P_3 IO_L19P_3 ...
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... VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT DS312-4 (v3.8) August 26, 2009 Product Specification XC3S500E Pin Name XC3S1200E Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. . Table 146: User I/Os Per Bank on XC3S1200E in the FT256 Package Package Maximum Edge I/O Bank ...