MAX2163ETI/V+T Maxim Integrated Products, MAX2163ETI/V+T Datasheet - Page 18

• Manufacturer Part Number: MAX2163ETI/V+T
• Description: RF Receiver Low power TV tuner f or 1 segment ISDB-T
• Manufacturer: Maxim Integrated Products

Specifications of MAX2163ETI/V+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX2163 has a 7-bit I
be sent to the device following a START condition to ini-
tiate communication. The slave address is internally
programmed to C0 or C2 for WRITE and C1 or C3 for
READ. See Table 2.
The MAX2163 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 1).
When addressed with a write command, the MAX2163
allows the master to write to a single register or to multi-
ple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX2163 issues an ACK
if the slave address byte is successfully received. The
bus master must then send the address of the first reg-
ister it wishes to write to (see Table 1 for register
addresses). The slave acknowledges the address, and
the master can then write one byte to the register at the
specified address. Data is written beginning with the
most significant bit (MSB). The MAX2163 again issues
an ACK if the data is successfully written to the register.
The master can continue to write data to the successive
internal registers with the MAX2163 acknowledging
each successful transfer, or the master can terminate
Figure 1. MAX2163 Slave Address Byte
Figure 2. Write Register 0 through 2 with 0x0E, 0x08, and 0xE1, respectively.
ISDB-T 1-Segment Tuner
18
START
______________________________________________________________________________________
WRITE 0B/CE
ADDRESS
1100000
SDR
SCL
R/W
0
3
ACK
2
—
C slave address that must
WRITE REGISTER
1
1
ADDRESS
0x00
Slave Address
Write Cycle
1
2
ACK
—
0
3
SLAVE ADDRESS
WRITE DATA TO
REGISTER 0x00
0
4
0x0E
0
transmission by issuing a STOP condition. The write
cycle does not terminate until the master issues a STOP
condition.
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0x08, and 0xE1,
respectively.
When addressed with a read command, the MAX2163
allows the master to read back a single register or mul-
tiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX2163 issues an ACK if
the slave address byte is successfully received. The bus
master must then send the address of the first register it
wishes to read (see Table 1 for register addresses). The
slave acknowledges the address. Then a START condi-
tion is issued by the master, followed by the 7 slave
address bits and a read bit (R/W = 1). The MAX2163
issues an ACK if the slave address byte is successfully
received. The MAX2163 starts sending data MSB first
with each SCL clock cycle. At the 9th clock cycle, the
master can issue an ACK and continue to read succes-
sive registers, or the master can terminate the transmis-
sion by issuing a NACK. The read cycle does not
terminate until the master issues a STOP condition.
Figure 3 illustrates an example in which registers 0
through 2 are read back.
5
ACK
—
1
6
WRITE DATA TO
REGISTER 0x01
0
7
0x0E
RIVAL
8
ACK
ACK
—
9
WRITE DATA TO
REGISTER 0x02
0xE1
Read Cycle
ACK
—
STOP