MAX2361EGM-D Maxim Integrated Products, MAX2361EGM-D Datasheet - Page 14

• Manufacturer Part Number: MAX2361EGM-D
• Description: RF Transmitter Complete Dual-Band Q uadrature Transmitte
• Manufacturer: Maxim Integrated Products

Specifications of MAX2361EGM-D

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Tables 11 and 12 show the typical cascaded perfor-
mance for TDMA and W-CDMA systems.
Figure 5 shows the 3-wire interface timing diagram. The
3-wire bus is SPI/QSPI/MICROWIRE compatible.
Two major concepts should be employed to produce a
low-spur and EMC-compliant transmitter: minimize cir-
cular current-loop area to reduce H-field radiation. To
minimize circular current-loop area, bypass as close to
Complete Dual-Band
Quadrature Transmitters
14
Figure 1. Register Configuration
______________________________________________________________________________________
CURRENT CONTROL REGISTER
CONFIGURATION REGISTER
RFM DIVIDE REGISTER
RFR DIVIDE REGISTER
IFM DIVIDE REGISTER
IFR DIVIDE REGISTER
CONTROL REGISTER
TEST REGISTER
Compliance Considerations
Cascaded Performance
B19
MSB
X
X
X
X
X
X
X
X
X = DON’T CARE
Electromagnetic
3-Wire Interface
B18
X
X
X
X
X
X
X
X
B17
B17
X
X
X
X
X
X
X
B16
B16
X
X
X
X
X
X
X
B15
B15
B15
B15
B15
X
X
X
X
B14
B14
B14
B14
B14
X
X
X
X
B13
B13
B13
B13
B13
B13 B12
X
X
X
B12
B12
B12
B12
B12
B12
X
X
B11
B11
B11
B11
B11
B11
B11
X
X
DATA 20 BITS
RFM DIVIDE RATIO (18)
OPERATION CONTROL BITS (16)
CURRENT CONTROL BITS (16)
B10
B10
B10
B10
B10
B10
B10
B10
the part as possible and use the distributed capaci-
tance of a ground plane. To minimize voltage drops,
make V
short.
Program only the necessary bits in any register to mini-
mize clock cycles. RC filtering can also be used to slow
the clock edges on the 3-wire interface, reducing high-
frequency spectral content. RC filtering also provides
for transient protection against IEC802 testing by shunt-
ing high frequencies to ground, while the series resis-
tance attenuates the transients for error-free operation.
The same applies to the logic input pins (SHDN,
TXGATE, IDLE).
CONFIGURATION BITS (16)
X
24 BIT REGISTER
B9
B9
B9
B9
B9
B9
B9
B9
X
IFM DIVIDE RATIO (14)
B8
B8
B8
B8
B8
B8
B8
B8
RFR DIVIDE RATIO (13)
B8
CC
B7
B7
B7
B7
B7
B7
B7
B7
B7
IFR DIVIDE RATIO (11)
traces short and wide, and make RF traces
B6
B6
B6
B6
B6
B6
B6
B6
B6
B5
B5
B5
B5
B5
B5
B5
B5
TEST BITS (9)
B5
B4
B4
B4
B4
B4
B4
B4
B4
B4
B3
B3
B3
B3
B3
B3
B3
B3
B3
B2
B2
B2
B2
B2
B2
B2
B2
B2
B1
B1
B1
B1
B1
B1
B1
B1
B1
B0
B0
B0
B0
B0
B0
B0
B0
B0
ADDRESS 4 BITS
A3
0
0
0
0
0
0
0
0
ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
LSB
A0
0
1
0
1
0
1
0
1