ATA6620N-TASY Atmel, ATA6620N-TASY Datasheet - Page 3

• Manufacturer Part Number: ATA6620N-TASY
• Description: RF Wireless Misc LIN SBC
• Manufacturer: Atmel

Specifications of ATA6620N-TASY

• Package / Case: SOIC
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. Functional Description
3.1
3.2
3.3
3.4
3.5
3.6
4850I–AUTO–09/09
Physical Layer Compatibility
Supply Pin (VS)
Ground Pin (GND)
Voltage Regulator Output Pin (VCC)
Undervoltage Reset Output (NRES)
Bus Pin (LIN)
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),
all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer
nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without
any restrictions.
LIN operating voltage is V
mode and the voltage regulator is switched on (that is, 5V/50 mA output capability).
The supply current in Sleep mode is typically 10 µA and 40 µA in Silent mode.
The IC is neutral on the LIN pin in case of GND disconnection. It is able to handle a ground shift
up to 3V for supply voltage above 9V at the VS pin.
The internal 5V voltage regulator is capable of driving loads with up to 50 mA, supplying the
microcontroller and other ICs on the PCB. It is protected against overload by means of current
limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will
cause a reset signal at the NRES output pin if it drops below a defined threshold V
This push-pull output is supplied from the V
voltage detection threshold of V
11) except the IC is switched into Sleep mode. Even if V
is internally driven from the V
V
The implemented undervoltage delay keeps NRES low for t
nominal value.
A low-side driver with internal current limitation and thermal shutdown, as well as an internal
pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from
–40V to +60V. This pin exhibits no reverse current from the LIN bus to V
GND shift or V
col specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are
slope controlled. The output has a short-circuit limitation. This is a self-adapting current limita-
tion; that is, during current limitation, as the chip temperature increases, the current decreases.
S
< 1.5V and then becomes highly resistive.
Batt
disconnection. The LIN receiver thresholds are compatible with the LIN proto-
S
= 5V to 18V. After switching on V
thun
S
voltage. If V
, NRES switches to low after tres_f (see
CC
voltage. If the V
S
voltage ramps down, NRES stays low until
CC
= 0V the NRES stays low, because it
S
Reset
, the IC starts with the Pre-normal
CC
= 10 ms after V
voltage falls below the under-
S
, even in the case of a
ATA6620N
Figure 4-7 on page
CC
thun
reaches its
.
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