CYS25G0101DX-ATXI Cypress Semiconductor Corp, CYS25G0101DX-ATXI Datasheet

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... Cypress Semiconductor Corporation Document Number: 38-02009 Rev. *K SONET OC-48 Transceiver Functional Description The CYS25G0101DX SONET OC-48 Transceiver is a commu- nications building block for high speed SONET data communica- tions. It provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and data recovery operations in a single chip optimized for full SONET compliance ...

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... LOOPA OUT ± Document Number: 38-02009 Rev. *K (155.52 MHz) ± REFCLK TXCLKO TX PLL X16 ÷ Bit-Clock Lock-to-Data/ Clock Control Logic PWRDN LOCKREF SD LFI CYS25G0101DX (155.52 MHz) RXCLK RXD[15:0] 16 Output Register ÷ 16 Shifter Recovered Bit-Clock RX CDR Retimed PLL Data Lock-to-Ref DIAGLOOP IN ± ...

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... ITU jitter requirements. Multiple loopback and loop through modes are available for both diagnostic and normal operation. For systems containing redundant SONET rings that are maintained in standby, the CYS25G0101DX may also be dynamically powered down to conserve system power. SONET Data Processor ...

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... Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ. Use VCCQ for compatibility with next generation of OC-48 SERDES devices. Document Number: 38-02009 Rev. *K [1, 2] Top View Top View CYS25G0101DX CYS25G0101DX CYS25G0101DX VCCQ VCCQ ...

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... The TXCLKI samples the data, TXD [15:0], on the rising edge of the clock cycle. TXCLKO HSTL Clock output Transmit Clock Output. Divide the selected transmit bit rate clock used to coordinate byte wide transfers between upstream logic and the CYS25G0101DX. V Input Analog Reference Voltage for HSTL Parallel Input Bus. V REF ...

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... CYS25G0101DX also provides various loopback functions. CYS25G0101DX Transmit Data Path Operating Modes The transmit path of the CYS25G0101DX supports 16-bit wide data paths. Phase Align Buffer Data from the input register is passed to a phase align buffer (FIFO). This buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock ...

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... Deserializer converts serial data into parallel data. RXD[15] is the most significant bit of the output word and is received first on the serial interface. Loopback Timing Modes CYS25G0101DX supports various loopback modes, as described in the following sections. Facility Loopback (Line Loopback with Retiming) When the LINELOOP signal is set HIGH, the Facility Loopback mode is activated and the high speed serial receive data (IN± ...

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... RESET and FIFO_RST signals should be asserted LOW along with PWRDN signal to ensure low power dissipation. LVPECL Compliance The CYS25G0101DX HSTL parallel I/O can be configured to LVPECL compliance with slight termination modifications. On the transmit side of the transceiver, the TXD[15:0] and TXCLKI are made LVPECL compliant by setting LVPECL signal – ...

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... Test Conditions Ω Referenced) 100 differential load V CC Ω Referenced) 100 differential load V Ω 100 differential load 100 Ω differential load Figure 3. Differential Waveform Definition )-V (-) CYS25G0101DX Typ Max Unit 300 347 [5] Min Max Unit 200 600 mV 400 1200 mV V – 1.2 V – ...

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... LVPECL Input Test Waveform 100Ω 100Ω 100Ω OUT+ ≤ (Includes fixture and OUT– probe capacitance) (b) CML AC Test Load CYS25G0101DX Min Max Unit V – 0.4 V DDQ 0.4 V 100 0. 0.3 V REF DDQ –0.3 V – 0.1 V REF µ ...

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... RXCLk rise time and fall times are measured at the percentile region of the rising and falling edge of the clock signal. 7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are shown in 8. +20 ppm is required to meet the SONET output frequency specification. ...

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... The Jitter Transfer Waveform of CYS25G0101DX follows. Figure 4. Jitter Transfer Waveform of CYS25G0101DX The Jitter Tolerance Waveform of CYS25G0101DX follows. Figure 5. Jitter Tolerance Waveform of CYS25G0101DX Notes 9. The RMS and P-to-P jitter values are measured using a 12 KHz to 20 MHz SONET filter. 10. Typical values are measured at room temperature and the Max values are measured at 0° C. ...

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... Figure 6. CYS25G0101DX Reference Clock Phase Noise Limits -75 -85 -95 -105 -115 -125 -135 -145 -155 1,000 Switching Waveforms Transmit Interface Timing TXCLKIDH TXCLKIDH TXCLKIDH TXCLKI TXCLKI TXDS TXDS TXDS TXDH TXDH TXDH TXD[15:0] TXD[15:0] TXCLKO TXCLKO Receive Interface Timing Document Number: 38-02009 Rev. *K ...

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... T Figure 11. LVPECL Compliant Output Termination VDDQ=3.3V RXD[15;0], 137 Ω RXCLK, TXCLKO OUTPUT CY S25G0101DX Note 13. Serial output of CYS25G0101DX is source matched to 50 Document Number: 38-02009 Rev. *K Figure 7. Serial Input Termination CY S25G0101DX Zo=50 Ω IN+ IN– Zo=50 Ω [13] Figure 8. Serial Output termination Optical Module Zo=50 Ω ...

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... Zo=50 Ω 0.1uF 130 Ω VCC 82 Ω 130 Ω Refcloc k I nter nall y Zo=50 Ω 82 Ω 0.1uF Figure 13. Clock Oscillator Termination CY S25G0101DX VCC Zo=50 Ω 130 Ω VCC 82 Ω 130 Ω Zo=50 Ω 82 Ω Reference Cloc k Input CYS25G0101DX Biased Page [+] Feedback ...

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... Ordering Information Speed Ordering Code Standard CYS25G0101DX-ATC Standard CYS25G0101DX-ATXC Standard CYS25G0101DX-ATI Standard CYS25G0101DX-ATXI Package Diagram Figure 14. 120-Pin Thin Quad Flatpack (14 × 14 × 1.4 mm) with Heat Slug AT120 Document Number: 38-02009 Rev. *K Package Name Package Type AT120 120-pin TQFP AT120 120-pin Pb-Free TQFP ...

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... Added power up requirements to Maximum Ratings information WAI Revised power up requirements Added Pb-free logo Added Pb-free parts to the Ordering Information: CYS25G0101DX-ATXC, CYS25G0101DX-ATXI Revised July 27, 2007 2 C components from Cypress or one of its sublicensed Associated Companies conveys a license under the 2 C Standard Specification as defined by Philips. All products and company names ...