CYS25G0101DX-ATXI Cypress Semiconductor Corp, CYS25G0101DX-ATXI Datasheet - Page 4

RF Transceiver BELLCORE SONET SDH OC 48 SERDES IND

CYS25G0101DX-ATXI

Manufacturer Part Number
CYS25G0101DX-ATXI
Description
RF Transceiver BELLCORE SONET SDH OC 48 SERDES IND
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYS25G0101DX-ATXI

Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Pin Configuration
Document Number: 38-02009 Rev. *K
Notes
The pin configuration for 120-pin Thin Quad Flatpack follows.
1. No connect (NC) pins are left unconnected or floating. Connecting any of these pins to the positive or negative power supply causes improper operation or failure of
2. Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ.
the device.
Use VCCQ for compatibility with next generation of OC-48 SERDES devices.
DIAG LOOP
DIAG LOOP
DIAG LOOP
LINELOO P
LINELOO P
LINELOO P
LOCKREF
LOCKREF
LOCKREF
RESET
RESET
RESET
LOOPA
LOOPA
LOOPA
RXCLK
RXCLK
RXCLK
R XD[0]
R XD[0]
R XD[0]
R XD[1]
R XD[1]
R XD[1]
R XD[2]
R XD[2]
R XD[2]
R XD[3]
R XD[3]
R XD[3]
R XD[4]
R XD[4]
R XD[4]
R XD[5]
R XD[5]
R XD[5]
R XD[6]
R XD[6]
R XD[6]
R XD[7]
R XD[7]
R XD[7]
VCCN
VCCN
VCCN
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
VSSN
LFI
LFI
LFI
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SD
SD
SD
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
9
9
9
10
10
10
11
11
11
12
12
12
13
13
13
14
14
14
15
15
15
16
16
16
17
17
17
18
18
18
19
19
19
20
20
20
21
21
21
22
22
22
23
23
23
24
24
24
25
25
25
26
26
26
27
27
27
28
28
28
29
29
29
30
30
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Figure 2. 120-Pin Thin Quad Flatpack Pin Configuration
CYS25G0101DX
CYS25G0101DX
Top View
Top View
[1, 2]
90
90
90
89
89
89
88
88
88
87
87
87
86
86
86
85
85
85
84
84
84
83
83
83
82
82
82
81
81
81
80
80
80
79
79
79
78
78
78
77
77
77
76
76
76
75
75
75
74
74
74
73
73
73
72
72
72
71
71
71
70
70
70
69
69
69
68
68
68
67
67
67
66
66
66
65
65
65
64
64
64
63
63
63
62
62
62
61
61
61
CYS25G0101DX
NC
NC
VCCQ
VCCQ
VSSQ
VSSQ
REFCLK+
REFCLK+
REFCLK–
REFCLK–
NC
NC
LO OPTIME
LO OPTIME
PW RDN
PW RDN
VCCN
VCCN
VSSN
VSSN
TXCLKO
TXCLKO
VDDQ
VDDQ
TXD[0]
TXD[0]
TXD[1]
TXD[1]
TXD[2]
TXD[2]
TXD[3]
TXD[3]
TXD[4]
TXD[4]
TXD[5]
TXD[5]
TXD[6]
TXD[6]
TXD[7]
TXD[7]
TXD[8]
TXD[8]
TXD[9]
TXD[9]
TXD[10]
TXD[10]
TXD[11]
TXD[11]
VSSN
VSSN
VSSN
VSSN
VCCQ
VCCQ
VSSQ
VSSQ
VCCN
VCCN
VSSN
VSSN
Page 4 of 17
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