ISPLSI 2128VE-100LQ160 LATTICE SEMICONDUCTOR, ISPLSI 2128VE-100LQ160 Datasheet

ISPLSI 2128VE-100LQ160

Manufacturer Part Number

ISPLSI 2128VE-100LQ160

Description

CPLD ispLSI® 2000VE Family 6K Gates 128 Macro Cells 100MHz EECMOS Technology 3.3V 160-Pin PQFP

Manufacturer

LATTICE SEMICONDUCTOR

Datasheet

1.ISPLSI_2128VE-100LQ160.pdf (20 pages)

Specifications of ISPLSI 2128VE-100LQ160

Package

160PQFP

Family Name

ispLSIÂ® 2000VE

Device System Gates

6000

Maximum Propagation Delay Time

10 ns

Number Of User I/os

128

Number Of Logic Blocks/elements

Typical Operating Supply Voltage

3.3 V

Maximum Operating Frequency

100 MHz

Operating Temperature

0 to 70 Â°C

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LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

• SuperFAST HIGH DENSITY IN-SYSTEM

• 3.3V LOW VOLTAGE 2128 ARCHITECTURE

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

• LEAD-FREE PACKAGE OPTIONS

2128ve_12

Features

PROGRAMMABLE LOGIC

— 6000 PLD Gates

— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs

— 128 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible

— Interfaces with Standard 5V TTL Devices

—

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— 3.3V In-System Programmability (ISP™) Using

— Open-Drain Output Option for Flexible Bus Interface

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Machines, Address Decoders, etc.

with ispLSI 2128V Devices

Boundary Scan Test Access Port (TAP)

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

Market and Improved Product Quality

Interconnectivity

max = 250MHz Maximum Operating Frequency

pd = 4.0ns Propagation Delay

CMOS

TECHNOLOGY

The ispLSI 2128VE is a High Density Programmable

Logic Device available in 128 and 64 I/O-pin versions.

The device contains 128 Registers, eight Dedicated

Input pins, three Dedicated Clock Input pins, two dedi-

cated Global OE input pins and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2128VE

features in-system programmability through the Bound-

ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2128VE

offers non-volatile reprogrammability of the logic, as well

as the interconnect to provide truly reconfigurable sys-

tems.

The basic unit of logic on the ispLSI 2128VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Functional Block Diagram*

Description

*128 I/O Version Shown

Output Routing Pool (ORP)

SuperFAST™ High Density PLD

ispLSI

3.3V In-System Programmable

Global Routing Pool (GRP)

Logic

Array

Output Routing Pool (ORP)

2128VE

GLB

August 2004

0139A/2128VE

Related parts for ISPLSI 2128VE-100LQ160

ISPLSI 2128VE-100LQ160 Summary of contents

Page 1

... The basic unit of logic on the ispLSI 2128VE device is the Generic Logic Block (GLB). The GLBs are labeled A0 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128VE device. Each GLB is made up of four macrocells ...

Page 2

... Functional Block Diagram Figure 1. ispLSI 2128VE Functional Block Diagram (128-I/O and 64-I/O Versions) RESET Input Bus GOE 0 GOE 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock I I/O 1 I/O 2 I I/O 5 I/O 6 I/O 7 I I/O 10 Global I/O 11 Routing I/O 12 ...

Page 3

... MHz) A SYMBOL PARAMETER C Dedicated Input Capacitance 1 C I/O Capacitance 2 C Clock and Global Output Enable Capacitance 3 Erase Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispLSI 2128VE 1 PARAMETER Commercial T = 0° 70°C A Industrial T = -40° 85°C A TYPICAL MINIMUM 10,000 3 MIN. ...

Page 4

... Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 2128VE Figure 2. Test Load GND to 3.0V ≤ 1.5ns 10% to 90% 1.5V 1.5V ...

Page 5

... External Synchronous Clock Pulse Duration, Low 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Specifications ispLSI 2128VE Over Recommended Operating Conditions 1 DESCRIPTION ...

Page 6

... External Synchronous Clock Pulse Duration, Low wl 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Specifications ispLSI 2128VE Over Recommended Operating Conditions 1 DESCRIPTION 2 1 ...

Page 7

... Global Reset to GLB gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 2128VE 1 Over Recommended Operating Conditions DESCRIPTION 3 ...

Page 8

Page 9

... Note: Calculations are based upon timing specifications for the ispLSI 2128VE-250L. Specifications ispLSI 2128VE GRP GLB Feedback Comb 4 PT Bypass #23 GRP Reg 4 PT Bypass GLB Reg Bypass #22 #24 ...

Page 10

... I CC can be estimated for the ispLSI 2128VE using the following equation PTs * 0.669 nets * max freq * 0.0026) Where PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The I CC estimate is based on typical conditions ( ...

Page 11

... When BSCAN is high, it functions as a dedicated input pin Dedicated Input Pins to the device. GND Ground (GND) VCC Vcc Connect I/O Input/Output Pins – These are the general purpose I/O pins used by the logic array pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 2128VE Description 11 ...

Page 12

... Signal Locations Specifications ispLSI 2128VE ...

Page 13

... M16 96 I/O 56 L15 98 I/O 57 L14 99 I/O 58 L16 100 I/O 59 K13 101 I/O 60 K15 102 I/O 61 K14 103 I/O 62 K16 104 I/O 63 J13 105 Specifications ispLSI 2128VE 208 160 100 100 Signal fpBGA caBGA TQFP I/O 64 H15 I/O 65 H13 I/O 66 G16 I/O 67 ...

Page 14

... Signal Configuration ispLSI 2128VE 208-Ball fpBGA Signal Diagram I/O I/O I I/O I I/O I/O I I/O I/O GND VCC I/O I/O I/O E VCC I/O I/O I/O F VCC I/O I/O I/O I I/O I GOE TCK/ I I/O I/O I/O I I/O I/O I/O L VCC I/O I/O I/O ...

Page 15

... Pin Configuration ispLSI 2128VE 176-Pin TQFP Pinout Diagram I/O 113 1 VCC 2 3 I/O 114 4 I/O 115 5 I/O 116 6 I/O 117 7 I/O 118 8 I/O 119 I/O 120 10 I/O 121 11 12 I/O 122 13 I/O 123 14 I/O 124 15 I/O 125 16 I/O 126 17 I/O 127 ...

Page 16

... Pin Configuration ispLSI 2128VE 160-Pin PQFP Pinout Diagram 1 I/O 113 2 VCC 3 I/O 114 4 I/O 115 5 I/O 116 I/O 117 6 I/O 118 7 8 I/O 119 9 I/O 120 10 I/O 121 11 I/O 122 12 I/O 123 13 I/O 124 I/O 125 14 I/O 126 15 16 I/O 127 ...

Page 17

... Signal Configuration ispLSI 2128VE 100-Ball caBGA Signal Diagram 10 9 I/O I I/O I I/O I I/O I GOE F VCC 0 TCK/ G GND IN 3 I/O I I/O I I/O I NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. Specifications ispLSI 2128VE ...

Page 18

... Pin Configuration ispLSI 2128VE 100-Pin TQFP Pinout Diagram RESET 11 VCC 12 GOE 1 13 GND 14 BSCAN 15 TDI pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 2128VE ispLSI 2128VE Top View I/O 34 ...

Page 19

... Grade Blank = Commercial I = Industrial Package Q160 = 160-Pin PQFP T176 = 176-Pin TQFP TN176 = Lead-Free 176-Pin TQFP ...

Page 20

... Ordering Information (Cont.) Conventional Packaging (Cont.) FAMILY fmax (MHz) tpd (ns) 135 7.5 ispLSI 135 7.5 Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 250 4.0 250 4.0 250 4.0 135 7.5 ispLSI 135 7.5 135 7.5 100 10 100 10 100 10 FAMILY fmax (MHz) ...

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