XC95144XL-10TQ144C Xilinx Inc, XC95144XL-10TQ144C Datasheet - Page 17

• Manufacturer Part Number: XC95144XL-10TQ144C
• Description: CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC95144XL-10TQ144C

• Package: 144TQFP
• Family Name: XC9500XL
• Device System Gates: 3200
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 117
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: 0 to 70 °C
• Case: TQFP144
• Dc: 04+/05+

Further Reading
Further information on the XC9500XL CPLD family can be found at:
http://www.xilinx.com/support/documentation/xc9500xl.htm.
This site includes:
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Revision History
The following table shows the revision history for this document.
DS054 (v2.5) May 22, 2009
Product Specification
09/28/98
10/02/98
02/03/99
04/02/99
06/07/99
06/07/99
01/25/02
02/07/03
08/02/04
11/11/04
07/15/05
03/22/06
07/25/06
04/03/07
11/20/08
05/22/09
Pinouts contained in the density-specific data sheets
Package electrical and thermal characteristics in UG112, Device Package User Guide
Termination, logic thresholds, power sequencing, and slew rate information in UG445, CPLD IO User Guide
Timing model in XAPP111, Using the XC9500XL Timing Model
Good design practices in XAPP784, Bulletproof CPLD Design Practices
Package drawings and dimensions at
Date
R
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
Initial Xilinx release.
Figure 1 correction.
Included hot socket reference; revised layout; BGA package change for XC95288XL.
Minor typesetting corrections.
Minor typesetting corrections.
Added CS280 package.
Added DS054 data sheet number. Added 44-pin VQFP package. Updated Device Family
table.
Added "Further Reading" section.
Added Pb-free documentation.
Changes to package designations in Table 2 on page 2.
Move to Product Specification.
Add Warranty Disclaimer.
Added Subthreshold State to Figure 17 and Table 5, page 16.
Added warning on programming temperature range, page 13.
Updated "Further Reading" section.
Updated description of power sequencing for 5V tolerance in "5V Tolerant I/Os" section.
http://www.xilinx.com/support/documentation/package_specifications.htm
www.xilinx.com
XC9500XL High-Performance CPLD Family Data Sheet
Revision
17