XC95144XL-10TQ144C Xilinx Inc, XC95144XL-10TQ144C Datasheet - Page 5

• Manufacturer Part Number: XC95144XL-10TQ144C
• Description: CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC95144XL-10TQ144C

• Package: 144TQFP
• Family Name: XC9500XL
• Device System Gates: 3200
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 117
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: 0 to 70 °C
• Case: TQFP144
• Dc: 04+/05+

All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
term clock. Both true and complement polarities of the
selected clock source can be used within each macrocell. A
GSR input is also provided to allow user registers to be set
to a user-defined state.
DS054 (v2.5) May 22, 2009
Product Specification
54
R
Figure
4, the macrocell register clock
Figure 3: XC9500XL Macrocell Within Function Block
Allocator
Product
Term
Additional
Product
Terms
(from other
macrocells)
Additional
Product
Terms
(from other
macrocells)
Product Term Clock Enable
Product Term Clock
Product Term Reset
Product Term Set
Product Term OE
1
0
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Set/Reset
Global
XC9500XL High-Performance CPLD Family Data Sheet
Clocks
3
Global
CE
D/T
R
S
Q
OUT
PTOE
To
FastCONNECTII
Switch Matrix
DS054_03_042101
To
I/O Blocks
5