UPD4991AGS Renesas Electronics America, UPD4991AGS Datasheet - Page 26

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UPD4991AGS

Manufacturer Part Number
UPD4991AGS
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD4991AGS

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24
Interval timer control block
(a) TP1 control (when D
iii) ALARM DISABLE (D
ii) ALARM FLAG (D
i) TP1 DISABLE (D
This bit controls output of TP1. When this bit is set, TP1 is forcibly turned OFF (high impedance)
regardless of the other operations.
This flag forcibly sets the alarm coincidence/non-coincidence status.
When this bit is set, the alarm coincidence status is set; when it is reset, the alarm non-coincidence
status is set.
This bit makes valid/invalid the alarm register and the result of comparison by the time counter. When
this bit is set, the result of comparison of alarm is ignored and the ALARM FLAG is not affected. If
ALARM DISABLE and ALARM FLAG are set, therefore, the alarm signal can be always output to TP1.
Clock
Time counter
Repeat/1 shot
Table 2-6. CONTROL REGISTER 2 Command List (W/O)
D
Interval
counter
0
1
3
3
0
1
)
)
= 0)
TP2 function control
2
)
Clock control
INTERVAL
0.1 s
CHAPTER 2 OPERATIONS
60 s
DISABLE
ALARM
STOP
BUSY
D
2
Control
register 2
Multi-
plexer
Select
INTERVAL
ALARM
RESET
FLAG
D
1
Output control
DISABLE
DISABLE
TP1
TP2
D
0
TP2 pin

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