IDT77V106L25TFI IDT, Integrated Device Technology Inc, IDT77V106L25TFI Datasheet
IDT77V106L25TFI
Specifications of IDT77V106L25TFI
Available stocks
Related parts for IDT77V106L25TFI
IDT77V106L25TFI Summary of contents
Page 1
ATM PHY for 25.6 and 51.2 Mbps FEATURES: • • • • • Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions of the Physical Layer • • • • • Compliant to ATM Forum (af-phy-040.000) ...
Page 2
IDT77V106L25 77V106L25 OVERVIEW The 77V106L25 is a physical layer interface chip for 25.6Mbps ATM network communications as defined by ATM Forum document af-phy-040.000 and ITU-T I.432.5. The physical layer is divided into a Physical Media Dependent sub layer (PMD) and ...
Page 3
IDT77V106L25 TABLE 1 — SIGNAL DESCRIPTION (PART Signal Name Pin Number I/O RXD+, RXD- 58 TXD+, TXD- 62, 61 Out Signal Name Pin Number I/O AD[7:0] 48, 47, 46, In/ 45, 43, 42, Out 41, ...
Page 4
IDT77V106L25 TABLE 1 — SIGNAL DESCRIPTION (PART Signal Name Pin Number I/O INT 34 Out OSC 52 In RST 35 In RXLED 33 Out RXREF 1 Out TXLED 3 Out TXREF ...
Page 5
IDT77V106L25 FUNCTIONAL DESCRIPTION Transmission Convergence (TC) Sub Layer Introduction The TC sub layer defines the line coding, scrambling, data framing and synchronization. Under control of a switch interface or Segmentation and Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a ...
Page 6
IDT77V106L25 3 Cells PHY-ATM Interface UTOPIA Control, Interface HEC Gen. & Insertion Start of Cell 4 4 Scrambler 4 Scramble Nibble Next PRNG 32MHz 64MHz Clock Input Figure 2. TC Transmit Block Diagram 6 TXRef (8kHz) Command Byte Insertion Reset ...
Page 7
IDT77V106L25 This encode/decode implementation has several very desirable properties. Among them is the fact that the output data bits can be represented by a set of relatively simple symbols; Run length is limited to <= 5; Disparity never exceeds +/- ...
Page 8
IDT77V106L25 PHY-ATM INTERFACE UTOPIA Level Physical (PHY) Layer to ATM Layer interface standardized by the ATM Forum used for transferring ATM cells and has separate transmit and receive channels and specific handshaking protocols ...
Page 9
IDT77V106L25 In the transmit direction, the PHY first asserts TXCLAV (transmit cell available) to indicate that it has room in its transmit FIFO to accept at least one 53-byte ATM cell. When the ATM layer device is ready to begin ...
Page 10
IDT77V106L25 TXCLK TXCLAV TXEN TXDATA[7:0], P42 P43 TXPARITY TXSOC Figure 6. Utopia Transmit Handshake - TXEN Suspended Transmission and Back to Back Cells (Octet Mode Only) TXCLK TXCLAV TXEN TXDATA[7:0], P47 P48 TXPARITY TXSOC Figure 7. Utopia Transmit Handshake - ...
Page 11
IDT77V106L25 CONTROL AND STATUS INTERFACE Utility Bus The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V106. These registers are used to select desired operating characteristics and functions, and to communicate status to external ...
Page 12
IDT77V106L25 LED CONTROL AND SIGNALING The LED outputs provide bi-directional LED drive capability example, the RxLED outputs are described in the truth table: State Pin Voltage Cells being received Low Cells not being received High ...
Page 13
IDT77V106L25 Loopback There are two loopback modes supported by the 77V106. The loopback mode is controlled via bits 1 and 0 of the Diagnostic Control Register. Bit 1 Bit Normal operating mode 1 0 PHY Loopback 1 ...
Page 14
IDT77V106L25 Counters Several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions anticipated that these counters will be polled from time to time (user selectable) to evaluate performance. • Symbol Error Counters ...
Page 15
IDT77V106L25 OSC Line Card 1 Normal Mode Loop Timing Jitter Specification TABLE 2 — LOOP TIMING JITTER Line Rate Data Rate Min. Mbps Mbps 32 25.6 — 100 ps 64 51.2 — 100 ps The waveforms below ...
Page 16
IDT77V106L25 Jitter at 25.6Mbps at point 4 with respect to point 1 Jitter at 51.2Mbps at point 4 with respect to point 1 From the above measurements taken, the amount of jitter being added at each TX point is not ...
Page 17
IDT77V106L25 LINE SIDE (SERIAL) INTERFACE PHY to Magnetics Interface A standard connection to 100Ω and 120Ω unshielded twisted pair cabling is shown in Figure 16. Note that the transmit signal is somewhat attenuated in order to meet the launch amplitude ...
Page 18
IDT77V106L25 TABLE 3 — ANALOG COMPONENT VALUES Component Value Tolerance R1 47Ω R2 47Ω R3 620Ω R4 110Ω (1) R5 10kΩ (1) R6 10kΩ R7 82Ω R8 33Ω R9 33Ω ±20% C1 470pFΩ ±20% C2 470pFΩ ±20% L1 3.3µH Note: ...
Page 19
IDT77V106L25 INTERRUPT STATUS REGISTER Address: 0x01 Bit Type Initial State Reserved Bad Signal Good Signal Bit. See definitions earlier in this data sheet 1 - Good Signal 1 - Bad Signal 5 sticky ...
Page 20
IDT77V106L25 LED DRIVER AND HEC STATUS/CONTROL REGISTER Address: 0x03 Bit Type Initial State Reserved 6 R enable Disable Receive HEC Checking (HEC Enable) Checking When not set, the HEC is calculated on first 4 bytes ...
Page 21
IDT77V106L25 INTERRUPT MASK REGISTER Address: 0x07 Bit Type Initial State 7 — 0 Reserved 6 — 0 Reserved 5 R Interrupt enable HEC Error Cell 4 R interrupt enable Short Cell Error 3 R ...
Page 22
IDT77V106L25 RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Ambient Industrial -40°C to +85°C CAPACITANCE (TA = +25° 1MHZ) Symbol Parameter C Input Capacitance IN C I/O Capacitance IO DC ELECTRICAL CHARACTERISTICS (ALL PINS EXCEPT TXD+/- AND RXD+/-) Symbol ...
Page 23
IDT77V106L25 UTOPIA BUS TIMING PARAMETERS Symbol t31 TxCLK Frequency t32 TxCLK Duty Cycle (% of t31) t33 TxDATA[7:0], TxPARITY Setup Time to TxCLK t34 TxDATA[7:0], TxPARITY Hold Time to TxCLK TxSCO, TxEN Setup Time to TxCLK t35 TxSOC, TxEN Hold ...
Page 24
IDT77V106L25 UTILITY BUS READ CYCLE Name Min Max Unit Tas 10 — ns Address Setup to ALE Tcsrd 0 — ns Chip select to read enable Tah 5 — ns Address hold to ALE Tapw 10 — ns ALE min ...
Page 25
IDT77V106L25 OSC, TXREF AND RESET TIMING Symbol Tcyc OSC cycle period (25.6 Mbps) (51.2 Mbps) Tckh OSC high time Tckl OSC low time Tcc OSC Cycle to cycle period variation TXREF High time Ttrh TXREF Low time Ttrl Minimum RST ...
Page 26
IDT77V106L25 PACKAGE DIMENSIONS SYMBOL ccc ddd Dimensions are in millimeters PSC-4046 is a more comprehensive package outline drawing which is available from the packaging section ...
Page 27
ORDERING INFORMATION IDT NNNNN A Device Type Power Note: Refer to the 77V406L25 Device Errata for an explanation of how to identify revisions and changes to revisions. REVISION HISTORY 4/29/99: PRELIMINARY. Initial release. 3/23/2000: PRELIMINARY. Various minor corrections. Change from ...